Hello community, here is the log from the commit of package libdrm for openSUSE:Factory checked in at 2012-12-07 14:37:55 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/libdrm (Old) and /work/SRC/openSUSE:Factory/.libdrm.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "libdrm", Maintainer is "sndir...@suse.com" Changes: -------- --- /work/SRC/openSUSE:Factory/libdrm/libdrm.changes 2012-10-03 07:58:10.000000000 +0200 +++ /work/SRC/openSUSE:Factory/.libdrm.new/libdrm.changes 2012-12-07 14:38:04.000000000 +0100 @@ -1,0 +2,30 @@ +Tue Nov 6 00:37:44 UTC 2012 - tobias.johannes.klausm...@mni.thm.de + +- Update to version 2.4.40: + + radeon: add some new SI pci ids + + radeon: fix unused-function warning + + intel: Fix "properly test for HAS_LLC" + + intel: Correct the word decoding for gen2 3DSTATE_LOAD_STATE_IMMEDIATE_1 + + configure.ac: Allow forcible disabling of Cairo support + + intel: properly test for HAS_LLC + + fix make distcheck + + vmwgfx: No longer experimental + + intel: add support for ValleyView + + libdrm: man page infrastructure and a few sample man pages + + intel: Mark bo's exported to prime as not reusable + + libkms: link against libdrm + + radeon: don't take the stencil-specific codepath for buffers without + stencil + + radeon: don't force stencil tile split to 0 + + radeon: fix stencil miptree allocation of combined ZS buffers on EG and + SI + + radeon: fix tile_split of 128-bit surface formats with 8x MSAA + + radeon: Fix layout of linear aligned mipmaps on SI. + + radeon: Memory footprint of SI mipmap base level is padded to powers of + two. + + radeon: Sampling pitch for non-mipmaps seems padded to slice alignment + on SI. + + initialize width/height fields in drmModeCrtc + + omap: release lock also on error paths + +------------------------------------------------------------------- Old: ---- libdrm-2.4.39.tar.bz2 New: ---- libdrm-2.4.40.tar.bz2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ libdrm.spec ++++++ --- /var/tmp/diff_new_pack.5BMndo/_old 2012-12-07 14:38:05.000000000 +0100 +++ /var/tmp/diff_new_pack.5BMndo/_new 2012-12-07 14:38:05.000000000 +0100 @@ -18,7 +18,7 @@ Name: libdrm Url: http://dri.freedesktop.org/ -Version: 2.4.39 +Version: 2.4.40 Release: 0 Provides: libdrm23 = %{version} Obsoletes: libdrm23 < %{version} @@ -162,7 +162,7 @@ %build export CFLAGS="$RPM_OPT_FLAGS -fno-strict-aliasing" autoreconf -fi -%configure --with-pic --enable-vmwgfx-experimental-api \ +%configure --with-pic \ %ifarch %arm --enable-omap-experimental-api \ %endif @@ -229,6 +229,7 @@ %_includedir/xf86drmMode.h %_libdir/libdrm*.so %_libdir/pkgconfig/libdrm*.pc +%_mandir/man3/drm* %files -n libdrm2 %defattr(-,root,root) ++++++ libdrm-2.4.39.tar.bz2 -> libdrm-2.4.40.tar.bz2 ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/.gitignore new/libdrm-2.4.40/.gitignore --- old/libdrm-2.4.39/.gitignore 2012-08-24 17:04:17.000000000 +0200 +++ new/libdrm-2.4.40/.gitignore 2012-11-06 01:23:53.000000000 +0100 @@ -42,6 +42,8 @@ libdrm_intel.pc libdrm_nouveau.pc libdrm_radeon.pc +libdrm_omap.pc +libdrm_exynos.pc libkms.pc libtool ltmain.sh @@ -76,3 +78,5 @@ tests/modetest/modetest tests/kmstest/kmstest tests/vbltest/vbltest +tests/radeon/radeon_ttm +man/*.3 diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/Makefile.am new/libdrm-2.4.40/Makefile.am --- old/libdrm-2.4.39/Makefile.am 2012-08-24 17:04:17.000000000 +0200 +++ new/libdrm-2.4.40/Makefile.am 2012-11-06 01:23:53.000000000 +0100 @@ -49,7 +49,7 @@ EXYNOS_SUBDIR = exynos endif -SUBDIRS = . $(LIBKMS_SUBDIR) $(INTEL_SUBDIR) $(NOUVEAU_SUBDIR) $(RADEON_SUBDIR) $(OMAP_SUBDIR) $(EXYNOS_SUBDIR) tests include +SUBDIRS = . $(LIBKMS_SUBDIR) $(INTEL_SUBDIR) $(NOUVEAU_SUBDIR) $(RADEON_SUBDIR) $(OMAP_SUBDIR) $(EXYNOS_SUBDIR) tests include man libdrm_la_LTLIBRARIES = libdrm.la libdrm_ladir = $(libdir) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/configure.ac new/libdrm-2.4.40/configure.ac --- old/libdrm-2.4.39/configure.ac 2012-08-24 17:04:17.000000000 +0200 +++ new/libdrm-2.4.40/configure.ac 2012-11-06 01:23:53.000000000 +0100 @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.39], + [2.4.40], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) @@ -35,6 +35,27 @@ # Enable quiet compiles on automake 1.11. m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])]) +if test x$LIB_MAN_SUFFIX = x ; then + LIB_MAN_SUFFIX=3 +fi +if test x$LIB_MAN_DIR = x ; then + LIB_MAN_DIR='$(mandir)/man$(LIB_MAN_SUFFIX)' +fi +AC_SUBST([LIB_MAN_SUFFIX]) +AC_SUBST([LIB_MAN_DIR]) + +MAN_SUBSTS="\ + -e 's|__vendorversion__|\"\$(PACKAGE_STRING)\" |' \ + -e 's|__projectroot__|\$(prefix)|g' \ + -e 's|__apploaddir__|\$(appdefaultdir)|g' \ + -e 's|__appmansuffix__|\$(APP_MAN_SUFFIX)|g' \ + -e 's|__drivermansuffix__|\$(DRIVER_MAN_SUFFIX)|g' \ + -e 's|__adminmansuffix__|\$(ADMIN_MAN_SUFFIX)|g' \ + -e 's|__libmansuffix__|\$(LIB_MAN_SUFFIX)|g' \ + -e 's|__miscmansuffix__|\$(MISC_MAN_SUFFIX)|g' \ + -e 's|__filemansuffix__|\$(FILE_MAN_SUFFIX)|g'" +AC_SUBST([MAN_SUBSTS]) + # Check for programs AC_PROG_CC @@ -78,10 +99,10 @@ [Enable support for nouveau's KMS API (default: auto)]), [NOUVEAU=$enableval], [NOUVEAU=auto]) -AC_ARG_ENABLE(vmwgfx-experimental-api, - AS_HELP_STRING([--enable-vmwgfx-experimental-api], - [Install vmwgfx's experimental kernel API header (default: disabled)]), - [VMWGFX=$enableval], [VMWGFX=no]) +AC_ARG_ENABLE(vmwgfx, + AS_HELP_STRING([--disable-vmwgfx], + [Enable support for vmwgfx's KMS API (default: yes)]), + [VMWGFX=$enableval], [VMWGFX=yes]) AC_ARG_ENABLE(omap-experimental-api, AS_HELP_STRING([--enable-omap-experimental-api], @@ -201,11 +222,23 @@ AC_DEFINE(HAVE_EXYNOS, 1, [Have EXYNOS support]) fi +AC_ARG_ENABLE([cairo-tests], + [AS_HELP_STRING([--enable-cairo-tests], + [Enable support for Cairo rendering in tests (default: auto)])], + [CAIRO=$enableval], [CAIRO=auto]) PKG_CHECK_MODULES(CAIRO, cairo, [HAVE_CAIRO=yes], [HAVE_CAIRO=no]) -if test "x$HAVE_CAIRO" = xyes; then - AC_DEFINE(HAVE_CAIRO, 1, [Have cairo support]) +AC_MSG_CHECKING([whether to enable Cairo tests]) +if test "x$CAIRO" = xauto; then + CAIRO="$HAVE_CAIRO" +fi +if test "x$CAIRO" = xyes; then + if ! test "x$HAVE_CAIRO" = xyes; then + AC_MSG_ERROR([Cairo support required but not present]) + fi + AC_DEFINE(HAVE_CAIRO, 1, [Have Cairo support]) fi -AM_CONDITIONAL(HAVE_CAIRO, [test "x$HAVE_CAIRO" = xyes]) +AC_MSG_RESULT([$CAIRO]) +AM_CONDITIONAL(HAVE_CAIRO, [test "x$CAIRO" = xyes]) # For enumerating devices in test case PKG_CHECK_MODULES(LIBUDEV, libudev, [HAVE_LIBUDEV=yes], [HAVE_LIBUDEV=no]) @@ -333,6 +366,7 @@ tests/vbltest/Makefile include/Makefile include/drm/Makefile + man/Makefile libdrm.pc]) AC_OUTPUT diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/intel/intel_bufmgr_gem.c new/libdrm-2.4.40/intel/intel_bufmgr_gem.c --- old/libdrm-2.4.39/intel/intel_bufmgr_gem.c 2012-08-24 17:04:17.000000000 +0200 +++ new/libdrm-2.4.40/intel/intel_bufmgr_gem.c 2012-11-06 01:23:53.000000000 +0100 @@ -2473,7 +2473,13 @@ drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; - return drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle, DRM_CLOEXEC, prime_fd); + if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle, + DRM_CLOEXEC, prime_fd) != 0) + return -errno; + + bo_gem->reusable = false; + + return 0; } static int @@ -3112,7 +3118,7 @@ bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) | IS_GEN7(bufmgr_gem->pci_device)); } else - bufmgr_gem->has_llc = ret == 0; + bufmgr_gem->has_llc = *gp.value; if (bufmgr_gem->gen < 4) { gp.param = I915_PARAM_NUM_FENCES_AVAIL; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/intel/intel_chipset.h new/libdrm-2.4.40/intel/intel_chipset.h --- old/libdrm-2.4.39/intel/intel_chipset.h 2012-08-24 17:04:17.000000000 +0200 +++ new/libdrm-2.4.40/intel/intel_chipset.h 2012-11-06 01:23:53.000000000 +0100 @@ -83,6 +83,8 @@ #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A +#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* power on board */ + #define IS_830(dev) (dev == 0x3577) #define IS_845(dev) (dev == 0x2562) #define IS_85X(dev) (dev == 0x3582) @@ -122,6 +124,8 @@ #define IS_I965GM(dev) (dev == 0x2A02) +#define IS_VALLEYVIEW(dev) (dev == 0xf30) + #define IS_GEN4(dev) (dev == 0x2972 || \ dev == 0x2982 || \ dev == 0x2992 || \ @@ -154,7 +158,8 @@ dev == PCI_CHIP_SANDYBRIDGE_S) #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ - IS_HASWELL(devid)) + IS_HASWELL(devid) || \ + IS_VALLEYVIEW(devid)) #define IS_IVYBRIDGE(dev) (dev == PCI_CHIP_IVYBRIDGE_GT1 || \ dev == PCI_CHIP_IVYBRIDGE_GT2 || \ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/intel/intel_decode.c new/libdrm-2.4.40/intel/intel_decode.c --- old/libdrm-2.4.39/intel/intel_decode.c 2012-08-24 17:04:17.000000000 +0200 +++ new/libdrm-2.4.40/intel/intel_decode.c 2012-11-06 01:23:53.000000000 +0100 @@ -1714,7 +1714,7 @@ } } else { instr_out(ctx, i, - "S%d: 0x%08x\n", i, data[i]); + "S%d: 0x%08x\n", word, data[i]); } i++; } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/libkms/Makefile.am new/libdrm-2.4.40/libkms/Makefile.am --- old/libdrm-2.4.39/libkms/Makefile.am 2012-08-24 17:04:17.000000000 +0200 +++ new/libdrm-2.4.40/libkms/Makefile.am 2012-11-06 01:23:53.000000000 +0100 @@ -6,7 +6,7 @@ libkms_la_LTLIBRARIES = libkms.la libkms_ladir = $(libdir) libkms_la_LDFLAGS = -version-number 1:0:0 -no-undefined -libkms_la_LIBADD = +libkms_la_LIBADD = ../libdrm.la #if HAVE_LIBUDEV #libkms_la_LIBADD += $(LIBUDEV_LIBS) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/man/Makefile.am new/libdrm-2.4.40/man/Makefile.am --- old/libdrm-2.4.39/man/Makefile.am 1970-01-01 01:00:00.000000000 +0100 +++ new/libdrm-2.4.40/man/Makefile.am 2012-11-06 01:23:53.000000000 +0100 @@ -0,0 +1,11 @@ +libmandir = $(LIB_MAN_DIR) +libman_PRE = drmAvailable.man \ + drmHandleEvent.man \ + drmModeGetResources.man +libman_DATA = $(libman_PRE:man=@LIB_MAN_SUFFIX@) +EXTRA_DIST = $(libman_PRE) +CLEANFILES = $(libman_DATA) +SUFFIXES = .$(LIB_MAN_SUFFIX) .man + +.man.$(LIB_MAN_SUFFIX): + $(AM_V_GEN)$(SED) $(MAN_SUBSTS) < $< > $@ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/man/drmAvailable.man new/libdrm-2.4.40/man/drmAvailable.man --- old/libdrm-2.4.39/man/drmAvailable.man 1970-01-01 01:00:00.000000000 +0100 +++ new/libdrm-2.4.40/man/drmAvailable.man 2012-11-06 01:23:53.000000000 +0100 @@ -0,0 +1,25 @@ +.\" shorthand for double quote that works everywhere. +.ds q \N'34' +.TH drmAvailable __drivermansuffix__ __vendorversion__ +.SH NAME +drmAvailable \- determine whether a DRM kernel driver has been loaded +.SH SYNOPSIS +.nf +.B "#include <xf86drm.h>" + +.B "int drmAvailable(void);" +.fi +.SH DESCRIPTION +This function allows the caller to determine whether a kernel DRM driver is +loaded. + +.SH RETURN VALUE +If a DRM driver is currently loaded, this function returns 1. Otherwise 0 +is returned. + +.SH REPORTING BUGS +Bugs in this function should be reported to http://bugs.freedesktop.org under +the "Mesa" product, with "Other" or "libdrm" as the component. + +.SH "SEE ALSO" +drmOpen(__libmansuffix__) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/man/drmHandleEvent.man new/libdrm-2.4.40/man/drmHandleEvent.man --- old/libdrm-2.4.39/man/drmHandleEvent.man 1970-01-01 01:00:00.000000000 +0100 +++ new/libdrm-2.4.40/man/drmHandleEvent.man 2012-11-06 01:23:53.000000000 +0100 @@ -0,0 +1,45 @@ +.\" shorthand for double quote that works everywhere. +.ds q \N'34' +.TH drmHandleEvent __drivermansuffix__ __vendorversion__ +.SH NAME +drmHandleEvent \- read and process pending DRM events +.SH SYNOPSIS +.nf +.B "#include <xf86drm.h>" + +.B "typedef struct _drmEventContext {" +.BI " int version;" +.BI " void (*vblank_handler)(int fd," +.BI " unsigned int sequence," +.BI " unsigned int tv_sec," +.BI " unsigned int tv_usec," +.BI " void *user_data);" +.BI " void (*page_flip_handler)(int fd," +.BI " unsigned int sequence," +.BI " unsigned int tv_sec," +.BI " unsigned int tv_usec," +.BI " void *user_data);" +.B "} drmEventContext, *drmEventContextPtr;" + +.B "int drmHandleEvent(int fd, drmEventContextPtr evctx);" +.fi +.SH DESCRIPTION +This function will process outstanding DRM events on +.I fd +, which must be an open DRM device. This function should be called after +the DRM file descriptor has polled readable; it will read the events and +use the passed-in +.I evctx +structure to call function pointers with the parameters noted above. + +.SH RETURN VALUE +Returns 0 on success, or if there is no data to read from the file descriptor. +Returns -1 if the read on the file descriptor fails or returns less than a +full event record. + +.SH REPORTING BUGS +Bugs in this function should be reported to http://bugs.freedesktop.org under +the "Mesa" product, with "Other" or "libdrm" as the component. + +.SH "SEE ALSO" +drmModePageFlip(__libmansuffix__), drmWaitVBlank(__libmansuffix__) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/man/drmModeGetResources.man new/libdrm-2.4.40/man/drmModeGetResources.man --- old/libdrm-2.4.39/man/drmModeGetResources.man 1970-01-01 01:00:00.000000000 +0100 +++ new/libdrm-2.4.40/man/drmModeGetResources.man 2012-11-06 01:23:53.000000000 +0100 @@ -0,0 +1,79 @@ +.\" shorthand for double quote that works everywhere. +.ds q \N'34' +.TH drmModeGetResources __drivermansuffix__ __vendorversion__ +.SH NAME +drmModeGetResources \- retrieve current display configuration information +.SH SYNOPSIS +.nf +.B "#include <xf86drmMode.h>" + +.BI "typedef struct _drmModeRes {" + +.BI " int count_fbs;" +.BI " uint32_t *fbs;" + +.BI " int count_crtcs;" +.BI " uint32_t *crtcs;" + +.BI " int count_connectors;" +.BI " uint32_t *connectors;" + +.BI " int count_encoders;" +.BI " uint32_t *encoders;" + +.BI " uint32_t min_width, max_width;" +.BI " uint32_t min_height, max_height;" +.B "} drmModeRes, *drmModeResPtr;" + +.B "drmModeResPtr drmModeGetResources(int fd);" +.fi +.SH DESCRIPTION +This function will allocate, populate, and return a drmModeRes structure +containing information about the current display configuration. + +The +.I count_fbs +and +.I fbs +fields indicate the number of currently allocated framebuffer objects (i.e. +objects that can be attached to a given CRTC or sprite for display). + +The +.I count_crtcs +and +.I crtcs +fields list the available CRTCs in the configuration. A CRTC is simply +an object that can scan out a framebuffer to a display sink, and contains +mode timing and relative position information. CRTCs drive encoders, which +are responsible for converting the pixel stream into a specific display +protocol (e.g. MIPI or HDMI). + +The +.I count_connectors +and +.I connectors +fields list the available physical connectors on the system. Note that +some of these may not be exposed from the chassis (e.g. LVDS or eDP). +Connectors are attached to encoders and contain information about the +attached display sink (e.g. width and height in mm, subpixel ordering, and +various other properties). + +The +.I count_encoders +and +.I encoders +fields list the available encoders on the device. Each encoder may be +associated with a CRTC, and may be used to drive a particular encoder. + +The min and max height fields indicate the maximum size of a framebuffer +for this device (i.e. the scanout size limit). + +.SH RETURN VALUE +Returns a drmModeRes structure pointer on success, 0 on failure. + +.SH REPORTING BUGS +Bugs in this function should be reported to http://bugs.freedesktop.org under +the "Mesa" product, with "Other" or "libdrm" as the component. + +.SH "SEE ALSO" +drmModeGetFB(__libmansuffix__), drmModeAddFB(__libmansuffix__), drmModeAddFB2(__libmansuffix__), drmModeRmFB(__libmansuffix__), drmModeDirtyFB(__libmansuffix__), drmModeGetCrtc(__libmansuffix__), drmModeSetCrtc(__libmansuffix__), drmModeGetEncoder(__libmansuffix__), drmModeGetConnector(__libmansuffix__) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/omap/omap_drm.c new/libdrm-2.4.40/omap/omap_drm.c --- old/libdrm-2.4.39/omap/omap_drm.c 2012-08-24 17:04:17.000000000 +0200 +++ new/libdrm-2.4.40/omap/omap_drm.c 2012-11-06 01:23:53.000000000 +0100 @@ -304,6 +304,7 @@ return bo; fail: + pthread_mutex_unlock(&table_lock); free(bo); return NULL; } @@ -337,6 +338,7 @@ return bo; fail: + pthread_mutex_unlock(&table_lock); free(bo); return NULL; } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/radeon/r600_pci_ids.h new/libdrm-2.4.40/radeon/r600_pci_ids.h --- old/libdrm-2.4.39/radeon/r600_pci_ids.h 2012-08-24 17:04:17.000000000 +0200 +++ new/libdrm-2.4.40/radeon/r600_pci_ids.h 2012-11-06 01:23:53.000000000 +0100 @@ -318,6 +318,8 @@ CHIPSET(0x6788, TAHITI_6788, TAHITI) CHIPSET(0x678A, TAHITI_678A, TAHITI) CHIPSET(0x6790, TAHITI_6790, TAHITI) +CHIPSET(0x6791, TAHITI_6791, TAHITI) +CHIPSET(0x6792, TAHITI_6792, TAHITI) CHIPSET(0x6798, TAHITI_6798, TAHITI) CHIPSET(0x6799, TAHITI_6799, TAHITI) CHIPSET(0x679A, TAHITI_679A, TAHITI) @@ -331,6 +333,7 @@ CHIPSET(0x6808, PITCAIRN_6808, PITCAIRN) CHIPSET(0x6809, PITCAIRN_6809, PITCAIRN) CHIPSET(0x6810, PITCAIRN_6810, PITCAIRN) +CHIPSET(0x6811, PITCAIRN_6811, PITCAIRN) CHIPSET(0x6816, PITCAIRN_6816, PITCAIRN) CHIPSET(0x6817, PITCAIRN_6817, PITCAIRN) CHIPSET(0x6818, PITCAIRN_6818, PITCAIRN) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/radeon/radeon_cs_gem.c new/libdrm-2.4.40/radeon/radeon_cs_gem.c --- old/libdrm-2.4.39/radeon/radeon_cs_gem.c 2012-08-24 17:04:17.000000000 +0200 +++ new/libdrm-2.4.40/radeon/radeon_cs_gem.c 2012-11-06 01:23:53.000000000 +0100 @@ -330,6 +330,7 @@ return 0; } +#if CS_BOF_DUMP static void cs_gem_dump_bof(struct radeon_cs_int *cs) { struct cs_gem *csg = (struct cs_gem*)cs; @@ -415,6 +416,7 @@ bof_decref(device_id); bof_decref(root); } +#endif static int cs_gem_emit(struct radeon_cs_int *cs) { diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/radeon/radeon_surface.c new/libdrm-2.4.40/radeon/radeon_surface.c --- old/libdrm-2.4.39/radeon/radeon_surface.c 2012-08-24 17:04:17.000000000 +0200 +++ new/libdrm-2.4.40/radeon/radeon_surface.c 2012-11-06 01:23:53.000000000 +0100 @@ -144,31 +144,32 @@ } static void surf_minify(struct radeon_surface *surf, - unsigned level, + struct radeon_surface_level *surflevel, + unsigned bpe, unsigned level, uint32_t xalign, uint32_t yalign, uint32_t zalign, unsigned offset) { - surf->level[level].npix_x = mip_minify(surf->npix_x, level); - surf->level[level].npix_y = mip_minify(surf->npix_y, level); - surf->level[level].npix_z = mip_minify(surf->npix_z, level); - surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; - surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; - surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; - if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D) { - if (surf->level[level].nblk_x < xalign || surf->level[level].nblk_y < yalign) { - surf->level[level].mode = RADEON_SURF_MODE_1D; + surflevel->npix_x = mip_minify(surf->npix_x, level); + surflevel->npix_y = mip_minify(surf->npix_y, level); + surflevel->npix_z = mip_minify(surf->npix_z, level); + surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; + surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; + surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d; + if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) { + if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) { + surflevel->mode = RADEON_SURF_MODE_1D; return; } } - surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, xalign); - surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, yalign); - surf->level[level].nblk_z = ALIGN(surf->level[level].nblk_z, zalign); + surflevel->nblk_x = ALIGN(surflevel->nblk_x, xalign); + surflevel->nblk_y = ALIGN(surflevel->nblk_y, yalign); + surflevel->nblk_z = ALIGN(surflevel->nblk_z, zalign); + + surflevel->offset = offset; + surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; + surflevel->slice_size = surflevel->pitch_bytes * surflevel->nblk_y; - surf->level[level].offset = offset; - surf->level[level].pitch_bytes = surf->level[level].nblk_x * surf->bpe * surf->nsamples; - surf->level[level].slice_size = surf->level[level].pitch_bytes * surf->level[level].nblk_y; - - surf->bo_size = offset + surf->level[level].slice_size * surf->level[level].nblk_z * surf->array_size; + surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; } /* =========================================================================== @@ -264,7 +265,7 @@ /* build mipmap tree */ for (i = start_level; i <= surf->last_level; i++) { surf->level[i].mode = RADEON_SURF_MODE_LINEAR; - surf_minify(surf, i, xalign, yalign, zalign, offset); + surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if ((i == 0)) { @@ -292,7 +293,7 @@ /* build mipmap tree */ for (i = start_level; i <= surf->last_level; i++) { surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED; - surf_minify(surf, i, xalign, yalign, zalign, offset); + surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if ((i == 0)) { @@ -325,7 +326,7 @@ /* build mipmap tree */ for (i = start_level; i <= surf->last_level; i++) { surf->level[i].mode = RADEON_SURF_MODE_1D; - surf_minify(surf, i, xalign, yalign, zalign, offset); + surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if ((i == 0)) { @@ -363,7 +364,7 @@ /* build mipmap tree */ for (i = start_level; i <= surf->last_level; i++) { surf->level[i].mode = RADEON_SURF_MODE_2D; - surf_minify(surf, i, xalign, yalign, zalign, offset); + surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); if (surf->level[i].mode == RADEON_SURF_MODE_1D) { return r6_surface_init_1d(surf_man, surf, offset, i); } @@ -543,6 +544,8 @@ } static void eg_surf_minify(struct radeon_surface *surf, + struct radeon_surface_level *surflevel, + unsigned bpe, unsigned level, unsigned slice_pt, unsigned mtilew, @@ -552,36 +555,38 @@ { unsigned mtile_pr, mtile_ps; - surf->level[level].npix_x = mip_minify(surf->npix_x, level); - surf->level[level].npix_y = mip_minify(surf->npix_y, level); - surf->level[level].npix_z = mip_minify(surf->npix_z, level); - surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; - surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; - surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; - if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D) { - if (surf->level[level].nblk_x < mtilew || surf->level[level].nblk_y < mtileh) { - surf->level[level].mode = RADEON_SURF_MODE_1D; + surflevel->npix_x = mip_minify(surf->npix_x, level); + surflevel->npix_y = mip_minify(surf->npix_y, level); + surflevel->npix_z = mip_minify(surf->npix_z, level); + surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; + surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; + surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d; + if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) { + if (surflevel->nblk_x < mtilew || surflevel->nblk_y < mtileh) { + surflevel->mode = RADEON_SURF_MODE_1D; return; } } - surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, mtilew); - surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, mtileh); - surf->level[level].nblk_z = ALIGN(surf->level[level].nblk_z, 1); + surflevel->nblk_x = ALIGN(surflevel->nblk_x, mtilew); + surflevel->nblk_y = ALIGN(surflevel->nblk_y, mtileh); + surflevel->nblk_z = ALIGN(surflevel->nblk_z, 1); /* macro tile per row */ - mtile_pr = surf->level[level].nblk_x / mtilew; + mtile_pr = surflevel->nblk_x / mtilew; /* macro tile per slice */ - mtile_ps = (mtile_pr * surf->level[level].nblk_y) / mtileh; + mtile_ps = (mtile_pr * surflevel->nblk_y) / mtileh; - surf->level[level].offset = offset; - surf->level[level].pitch_bytes = surf->level[level].nblk_x * surf->bpe * slice_pt; - surf->level[level].slice_size = mtile_ps * mtileb * slice_pt; + surflevel->offset = offset; + surflevel->pitch_bytes = surflevel->nblk_x * bpe * slice_pt; + surflevel->slice_size = mtile_ps * mtileb * slice_pt; - surf->bo_size = offset + surf->level[level].slice_size * surf->level[level].nblk_z * surf->array_size; + surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; } static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, + struct radeon_surface_level *level, + unsigned bpe, uint64_t offset, unsigned start_level) { uint32_t xalign, yalign, zalign, tilew; @@ -589,45 +594,40 @@ /* compute alignment */ tilew = 8; - xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); - if (surf->flags & RADEON_SURF_SBUFFER) { - xalign = surf_man->hw_info.group_bytes / (tilew * surf->nsamples); - } + xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples); xalign = MAX2(tilew, xalign); yalign = tilew; zalign = 1; if (surf->flags & RADEON_SURF_SCANOUT) { - xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); + xalign = MAX2((bpe == 1) ? 64 : 32, xalign); } + if (!start_level) { - surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); + unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes); + surf->bo_alignment = MAX2(surf->bo_alignment, alignment); + + if (offset) { + offset = ALIGN(offset, alignment); + } } /* build mipmap tree */ for (i = start_level; i <= surf->last_level; i++) { - surf->level[i].mode = RADEON_SURF_MODE_1D; - surf_minify(surf, i, xalign, yalign, zalign, offset); + level[i].mode = RADEON_SURF_MODE_1D; + surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, offset); /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if ((i == 0)) { offset = ALIGN(offset, surf->bo_alignment); } } - - /* The depth and stencil buffers are in separate resources on evergreen. - * We allocate them in one buffer next to each other to simplify - * communication between the DDX and the Mesa driver. */ - if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) == - (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { - surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); - surf->bo_size = surf->stencil_offset + surf->bo_size / 4; - } - return 0; } static int eg_surface_init_2d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, + struct radeon_surface_level *level, + unsigned bpe, unsigned tile_split, uint64_t offset, unsigned start_level) { unsigned tilew, tileh, tileb; @@ -638,11 +638,11 @@ /* compute tile values */ tilew = 8; tileh = 8; - tileb = tilew * tileh * surf->bpe * surf->nsamples; + tileb = tilew * tileh * bpe * surf->nsamples; /* slices per tile */ slice_pt = 1; - if (tileb > surf->tile_split) { - slice_pt = tileb / surf->tile_split; + if (tileb > tile_split) { + slice_pt = tileb / tile_split; } tileb = tileb / slice_pt; @@ -653,15 +653,20 @@ mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb; if (!start_level) { - surf->bo_alignment = MAX2(256, mtileb); + unsigned alignment = MAX2(256, mtileb); + surf->bo_alignment = MAX2(surf->bo_alignment, alignment); + + if (offset) { + offset = ALIGN(offset, alignment); + } } /* build mipmap tree */ for (i = start_level; i <= surf->last_level; i++) { - surf->level[i].mode = RADEON_SURF_MODE_2D; - eg_surf_minify(surf, i, slice_pt, mtilew, mtileh, mtileb, offset); - if (surf->level[i].mode == RADEON_SURF_MODE_1D) { - return eg_surface_init_1d(surf_man, surf, offset, i); + level[i].mode = RADEON_SURF_MODE_2D; + eg_surf_minify(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, mtileb, offset); + if (level[i].mode == RADEON_SURF_MODE_1D) { + return eg_surface_init_1d(surf_man, surf, level, bpe, offset, i); } /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; @@ -669,13 +674,6 @@ offset = ALIGN(offset, surf->bo_alignment); } } - - if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) == - (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { - surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); - surf->bo_size = surf->stencil_offset + surf->bo_size / 4; - } - return 0; } @@ -762,6 +760,51 @@ return 0; } +static int eg_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf) +{ + unsigned zs_flags = RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER; + int r, is_depth_stencil = (surf->flags & zs_flags) == zs_flags; + /* Old libdrm headers didn't have stencil_level in it. This prevents crashes. */ + struct radeon_surface_level tmp[RADEON_SURF_MAX_LEVEL]; + struct radeon_surface_level *stencil_level = + (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp; + + r = eg_surface_init_1d(surf_man, surf, surf->level, surf->bpe, 0, 0); + if (r) + return r; + + if (is_depth_stencil) { + r = eg_surface_init_1d(surf_man, surf, stencil_level, 1, + surf->bo_size, 0); + surf->stencil_offset = stencil_level[0].offset; + } + return r; +} + +static int eg_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf) +{ + unsigned zs_flags = RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER; + int r, is_depth_stencil = (surf->flags & zs_flags) == zs_flags; + /* Old libdrm headers didn't have stencil_level in it. This prevents crashes. */ + struct radeon_surface_level tmp[RADEON_SURF_MAX_LEVEL]; + struct radeon_surface_level *stencil_level = + (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp; + + r = eg_surface_init_2d(surf_man, surf, surf->level, surf->bpe, + surf->tile_split, 0, 0); + if (r) + return r; + + if (is_depth_stencil) { + r = eg_surface_init_2d(surf_man, surf, stencil_level, 1, + surf->stencil_tile_split, surf->bo_size, 0); + surf->stencil_offset = stencil_level[0].offset; + } + return r; +} + static int eg_surface_init(struct radeon_surface_manager *surf_man, struct radeon_surface *surf) { @@ -797,7 +840,7 @@ } surf->stencil_offset = 0; - surf->stencil_tile_split = 0; + surf->bo_alignment = 0; /* check tiling mode */ switch (mode) { @@ -808,10 +851,10 @@ r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0); break; case RADEON_SURF_MODE_1D: - r = eg_surface_init_1d(surf_man, surf, 0, 0); + r = eg_surface_init_1d_miptrees(surf_man, surf); break; case RADEON_SURF_MODE_2D: - r = eg_surface_init_2d(surf_man, surf, 0, 0); + r = eg_surface_init_2d_miptrees(surf_man, surf); break; default: return -EINVAL; @@ -896,6 +939,8 @@ } else { /* tile split must be >= 256 for colorbuffer surfaces */ surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256); + if (surf->tile_split > 4096) + surf->tile_split = 4096; } } else { /* set tile split to row size */ @@ -911,7 +956,7 @@ * fmask buffer has different optimal value figure them out once we * use it. */ - if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { + if (surf->flags & RADEON_SURF_SBUFFER) { /* assume 1 bytes for stencil, we optimize for stencil as stencil * and depth shares surface values */ @@ -952,6 +997,136 @@ /* =========================================================================== + * Southern Islands family + */ + +static void si_surf_minify_linear_aligned(struct radeon_surface *surf, + unsigned level, + uint32_t xalign, uint32_t yalign, uint32_t zalign, uint32_t slice_align, + unsigned offset) +{ + surf->level[level].npix_x = mip_minify(surf->npix_x, level); + surf->level[level].npix_y = mip_minify(surf->npix_y, level); + surf->level[level].npix_z = mip_minify(surf->npix_z, level); + + if (level == 0 && surf->last_level > 0) { + surf->level[level].nblk_x = (next_power_of_two(surf->level[level].npix_x) + surf->blk_w - 1) / surf->blk_w; + surf->level[level].nblk_y = (next_power_of_two(surf->level[level].npix_y) + surf->blk_h - 1) / surf->blk_h; + surf->level[level].nblk_z = (next_power_of_two(surf->level[level].npix_z) + surf->blk_d - 1) / surf->blk_d; + } else { + surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; + surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; + surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; + } + + /* XXX: Texture sampling uses unexpectedly large pitches in some cases, + * these are just guesses for the rules behind those + */ + if (level == 0 && surf->last_level == 0) + /* Non-mipmap pitch padded to slice alignment */ + xalign = MAX2(xalign, slice_align / surf->bpe); + else + /* Small rows evenly distributed across slice */ + xalign = MAX2(xalign, slice_align / surf->bpe / surf->level[level].npix_y); + + surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, xalign); + surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, yalign); + surf->level[level].nblk_z = ALIGN(surf->level[level].nblk_z, zalign); + + surf->level[level].offset = offset; + surf->level[level].pitch_bytes = surf->level[level].nblk_x * surf->bpe * surf->nsamples; + surf->level[level].slice_size = ALIGN(surf->level[level].pitch_bytes * surf->level[level].nblk_y, slice_align); + + surf->bo_size = offset + surf->level[level].slice_size * surf->level[level].nblk_z * surf->array_size; +} + +static int si_surface_init_linear_aligned(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf, + uint64_t offset, unsigned start_level) +{ + uint32_t xalign, yalign, zalign, slice_align; + unsigned i; + + /* compute alignment */ + if (!start_level) { + surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); + } + xalign = MAX2(8, 64 / surf->bpe); + yalign = 1; + zalign = 1; + slice_align = MAX2(64 * surf->bpe, surf_man->hw_info.group_bytes); + + /* build mipmap tree */ + for (i = start_level; i <= surf->last_level; i++) { + surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED; + si_surf_minify_linear_aligned(surf, i, xalign, yalign, zalign, slice_align, offset); + /* level0 and first mipmap need to have alignment */ + offset = surf->bo_size; + if ((i == 0)) { + offset = ALIGN(offset, surf->bo_alignment); + } + } + return 0; +} + +static int si_surface_init(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf) +{ + unsigned mode; + int r; + + /* MSAA surfaces support the 2D mode only. */ + if (surf->nsamples > 1) { + surf->flags = RADEON_SURF_CLR(surf->flags, MODE); + surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); + } + + /* tiling mode */ + mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; + + if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { + /* zbuffer only support 1D or 2D tiled surface */ + switch (mode) { + case RADEON_SURF_MODE_1D: + case RADEON_SURF_MODE_2D: + break; + default: + mode = RADEON_SURF_MODE_1D; + surf->flags = RADEON_SURF_CLR(surf->flags, MODE); + surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); + break; + } + } + + r = eg_surface_sanity(surf_man, surf, mode); + if (r) { + return r; + } + + surf->stencil_offset = 0; + surf->bo_alignment = 0; + + /* check tiling mode */ + switch (mode) { + case RADEON_SURF_MODE_LINEAR: + r = r6_surface_init_linear(surf_man, surf, 0, 0); + break; + case RADEON_SURF_MODE_LINEAR_ALIGNED: + r = si_surface_init_linear_aligned(surf_man, surf, 0, 0); + break; + case RADEON_SURF_MODE_1D: + r = eg_surface_init_1d_miptrees(surf_man, surf); + break; + case RADEON_SURF_MODE_2D: + r = eg_surface_init_2d_miptrees(surf_man, surf); + break; + default: + return -EINVAL; + } + return r; +} + +/* =========================================================================== * public API */ struct radeon_surface_manager *radeon_surface_manager_new(int fd) @@ -980,7 +1155,11 @@ if (eg_init_hw_info(surf_man)) { goto out_err; } - surf_man->surface_init = &eg_surface_init; + if (surf_man->family <= CHIP_ARUBA) { + surf_man->surface_init = &eg_surface_init; + } else { + surf_man->surface_init = &si_surface_init; + } surf_man->surface_best = &eg_surface_best; } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/radeon/radeon_surface.h new/libdrm-2.4.40/radeon/radeon_surface.h --- old/libdrm-2.4.39/radeon/radeon_surface.h 2012-08-24 17:04:17.000000000 +0200 +++ new/libdrm-2.4.40/radeon/radeon_surface.h 2012-11-06 01:23:53.000000000 +0100 @@ -54,6 +54,7 @@ #define RADEON_SURF_SCANOUT (1 << 16) #define RADEON_SURF_ZBUFFER (1 << 17) #define RADEON_SURF_SBUFFER (1 << 18) +#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19) #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK) #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) @@ -102,6 +103,7 @@ uint32_t stencil_tile_split; uint64_t stencil_offset; struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL]; + struct radeon_surface_level stencil_level[RADEON_SURF_MAX_LEVEL]; }; struct radeon_surface_manager *radeon_surface_manager_new(int fd); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/tests/modetest/Makefile.am new/libdrm-2.4.40/tests/modetest/Makefile.am --- old/libdrm-2.4.39/tests/modetest/Makefile.am 2012-08-24 17:04:17.000000000 +0200 +++ new/libdrm-2.4.40/tests/modetest/Makefile.am 2012-11-06 01:23:53.000000000 +0100 @@ -1,8 +1,7 @@ AM_CFLAGS = \ -I$(top_srcdir)/include/drm \ -I$(top_srcdir)/libkms/ \ - -I$(top_srcdir) \ - $(CAIRO_CFLAGS) + -I$(top_srcdir) noinst_PROGRAMS = \ modetest @@ -12,5 +11,9 @@ modetest_LDADD = \ $(top_builddir)/libdrm.la \ - $(top_builddir)/libkms/libkms.la \ - $(CAIRO_LIBS) + $(top_builddir)/libkms/libkms.la + +if HAVE_CAIRO +AM_CFLAGS += $(CAIRO_CFLAGS) +modetest_LDADD += $(CAIRO_LIBS) +endif diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.39/xf86drmMode.c new/libdrm-2.4.40/xf86drmMode.c --- old/libdrm-2.4.39/xf86drmMode.c 2012-08-24 17:04:17.000000000 +0200 +++ new/libdrm-2.4.40/xf86drmMode.c 2012-11-06 01:23:53.000000000 +0100 @@ -351,8 +351,11 @@ r->x = crtc.x; r->y = crtc.y; r->mode_valid = crtc.mode_valid; - if (r->mode_valid) + if (r->mode_valid) { memcpy(&r->mode, &crtc.mode, sizeof(struct drm_mode_modeinfo)); + r->width = crtc.mode.hdisplay; + r->height = crtc.mode.vdisplay; + } r->buffer_id = crtc.fb_id; r->gamma_size = crtc.gamma_size; return r; -- To unsubscribe, e-mail: opensuse-commit+unsubscr...@opensuse.org For additional commands, e-mail: opensuse-commit+h...@opensuse.org
