Hello community, here is the log from the commit of package mcelog for openSUSE:Factory checked in at 2016-05-11 16:37:14 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/mcelog (Old) and /work/SRC/openSUSE:Factory/.mcelog.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "mcelog" Changes: -------- --- /work/SRC/openSUSE:Factory/mcelog/mcelog.changes 2016-02-12 11:21:15.000000000 +0100 +++ /work/SRC/openSUSE:Factory/.mcelog.new/mcelog.changes 2016-05-11 16:37:15.000000000 +0200 @@ -1,0 +2,6 @@ +Fri May 6 16:08:48 UTC 2016 - [email protected] + +- Update to bugfix version 1.36 +- Do not start mcelog service based on an udev (/dev/mcelog) rule (bsc#976781) + +------------------------------------------------------------------- Old: ---- 90-mcelog.rules mcelog-1.29.tar.bz2 New: ---- mcelog-1.36.tar.bz2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ mcelog.spec ++++++ --- /var/tmp/diff_new_pack.mi1bOK/_old 2016-05-11 16:37:17.000000000 +0200 +++ /var/tmp/diff_new_pack.mi1bOK/_new 2016-05-11 16:37:17.000000000 +0200 @@ -17,7 +17,7 @@ Name: mcelog -Version: 1.29 +Version: 1.36 Release: 0 Summary: Log Machine Check Events License: GPL-2.0 @@ -26,7 +26,6 @@ Source: mcelog-%{version}.tar.bz2 Source2: mcelog.sysconfig Source3: mcelog.systemd -Source4: 90-mcelog.rules Source5: mcelog.tmpfiles Source6: README.email_setup Patch1: email.patch @@ -43,7 +42,6 @@ Patch12: fix_setgroups_missing_call.patch BuildRequires: libesmtp-devel BuildRequires: pkgconfig(systemd) -BuildRequires: pkgconfig(udev) Requires: logrotate Requires(pre): %fillup_prereq # Previously version was wrong, mainline decided to go for 1.0.1. not 1.1 @@ -95,7 +93,6 @@ install -m 644 %{SOURCE6} %{buildroot}/%{_docdir}/%{name}/README.email_setup install -m 644 lk10-mcelog.pdf %{buildroot}/%{_docdir}/%{name}/lk10-mcelog.pdf install -D -m 0644 %{SOURCE3} %{buildroot}%{_unitdir}/mcelog.service -install -D -m 0644 %{SOURCE4} %{buildroot}%{_udevrulesdir}/90-mcelog.rules install -D -m 0644 %{SOURCE5} %{buildroot}%{_tmpfilesdir}/mcelog.conf ln -sf %{_sbindir}/service %{buildroot}%{_sbindir}/rcmcelog @@ -104,7 +101,6 @@ %post %fillup_only -%udev_rules_update %service_add_post %{name}.service %{?tmpfiles_create:%tmpfiles_create %{_tmpfilesdir}/mcelog.conf} @@ -125,7 +121,6 @@ %{_localstatedir}/adm/fillup-templates/sysconfig.mcelog %{_sysconfdir}/mcelog/*trigger %{_unitdir}/mcelog.service -%{_udevrulesdir}/90-mcelog.rules %{_tmpfilesdir}/mcelog.conf %{_docdir}/%{name} %{_sbindir}/rcmcelog ++++++ Start-consolidating-AMD-specific-stuff.patch ++++++ --- /var/tmp/diff_new_pack.mi1bOK/_old 2016-05-11 16:37:17.000000000 +0200 +++ /var/tmp/diff_new_pack.mi1bOK/_new 2016-05-11 16:37:17.000000000 +0200 @@ -16,10 +16,10 @@ rename k8.c => amd.c (97%) rename k8.h => amd.h (79%) -Index: mcelog-1.29/Makefile +Index: mcelog-1.36/Makefile =================================================================== ---- mcelog-1.29.orig/Makefile 2016-01-28 15:33:45.402475555 +0100 -+++ mcelog-1.29/Makefile 2016-01-28 15:33:51.646831409 +0100 +--- mcelog-1.36.orig/Makefile 2016-05-03 17:44:06.934899300 +0200 ++++ mcelog-1.36/Makefile 2016-05-03 17:44:29.032158410 +0200 @@ -33,7 +33,7 @@ all: mcelog .PHONY: install clean depend FORCE @@ -29,9 +29,9 @@ nehalem.o dunnington.o tulsa.o config.o memutil.o msg.o \ eventloop.o leaky-bucket.o memdb.o server.o trigger.o \ client.o cache.o sysfs.o yellow.o page.o rbtree.o \ -Index: mcelog-1.29/k8.c +Index: mcelog-1.36/k8.c =================================================================== ---- mcelog-1.29.orig/k8.c 2016-01-20 18:33:20.000000000 +0100 +--- mcelog-1.36.orig/k8.c 2016-05-03 17:44:06.938899528 +0200 +++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,281 +0,0 @@ -/* Based on K8 decoding code written for the 2.4 kernel by Andi Kleen and @@ -125,7 +125,7 @@ - [0] = "err cpu0", -}; -static char *k8threshold[] = { -- [0 ... K8_MCELOG_THRESHOLD_DRAM_ECC - 1] = "Unknow threshold counter", +- [0 ... K8_MCELOG_THRESHOLD_DRAM_ECC - 1] = "Unknown threshold counter", - [K8_MCELOG_THRESHOLD_DRAM_ECC] = "MC4_MISC0 DRAM threshold", - [K8_MCELOG_THRESHOLD_LINK] = "MC4_MISC1 Link threshold", - [K8_MCELOG_THRESHOLD_L3_CACHE] = "MC4_MISC2 L3 Cache threshold", @@ -315,10 +315,10 @@ - } - return 1; -} -Index: mcelog-1.29/amd.c +Index: mcelog-1.36/amd.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ mcelog-1.29/amd.c 2016-01-28 15:33:51.646831409 +0100 ++++ mcelog-1.36/amd.c 2016-05-03 17:44:29.036158703 +0200 @@ -0,0 +1,282 @@ +/* Based on K8 decoding code written for the 2.4 kernel by Andi Kleen and + * Eric Morton. Hacked and extended for mcelog by AK. @@ -602,9 +602,9 @@ + } + return 1; +} -Index: mcelog-1.29/k8.h +Index: mcelog-1.36/k8.h =================================================================== ---- mcelog-1.29.orig/k8.h 2016-01-20 18:33:20.000000000 +0100 +--- mcelog-1.36.orig/k8.h 2016-05-03 17:44:06.938899528 +0200 +++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,11 +0,0 @@ -char *k8_bank_name(unsigned num); @@ -618,10 +618,10 @@ -#define K8_MCELOG_THRESHOLD_LINK (4 * 9 + 1) -#define K8_MCELOG_THRESHOLD_L3_CACHE (4 * 9 + 2) -#define K8_MCELOG_THRESHOLD_FBDIMM (4 * 9 + 3) -Index: mcelog-1.29/amd.h +Index: mcelog-1.36/amd.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ mcelog-1.29/amd.h 2016-01-28 15:33:51.650831636 +0100 ++++ mcelog-1.36/amd.h 2016-05-03 17:44:29.036158703 +0200 @@ -0,0 +1,14 @@ +char *k8_bank_name(unsigned num); +void decode_amd_mc(enum cputype, struct mce *mce, int *ismemerr); @@ -637,10 +637,10 @@ + +#define CASE_AMD_CPUS \ + case CPU_K8 -Index: mcelog-1.29/mcelog.c +Index: mcelog-1.36/mcelog.c =================================================================== ---- mcelog-1.29.orig/mcelog.c 2016-01-28 15:33:45.406475783 +0100 -+++ mcelog-1.29/mcelog.c 2016-01-28 15:33:51.650831636 +0100 +--- mcelog-1.36.orig/mcelog.c 2016-05-03 17:44:06.938899528 +0200 ++++ mcelog-1.36/mcelog.c 2016-05-03 17:44:29.036158703 +0200 @@ -41,7 +41,7 @@ #include <fnmatch.h> #include "mcelog.h" @@ -650,7 +650,7 @@ #include "intel.h" #include "p4.h" #include "dmi.h" -@@ -419,9 +419,9 @@ static void dump_mce(struct mce *m, unsi +@@ -421,9 +421,9 @@ static void dump_mce(struct mce *m, unsi time_t t = m->time; Wprintf("TIME %llu %s", m->time, ctime(&t)); } ++++++ add-f10h-support.patch ++++++ --- /var/tmp/diff_new_pack.mi1bOK/_old 2016-05-11 16:37:17.000000000 +0200 +++ /var/tmp/diff_new_pack.mi1bOK/_new 2016-05-11 16:37:17.000000000 +0200 @@ -1,10 +1,10 @@ Add F10h decoding support Signed-off-by: Borislav Petkov <[email protected]> -Index: mcelog-1.20/amd.c +Index: mcelog-1.36/amd.c =================================================================== ---- mcelog-1.20.orig/amd.c 2015-06-15 15:16:07.712107628 +0200 -+++ mcelog-1.20/amd.c 2015-06-15 15:16:14.564499430 +0200 +--- mcelog-1.36.orig/amd.c 2016-05-03 17:45:20.771106536 +0200 ++++ mcelog-1.36/amd.c 2016-05-03 17:45:35.943971068 +0200 @@ -14,7 +14,7 @@ #include "mcelog.h" #include "amd.h" @@ -14,7 +14,7 @@ "data cache", "instruction cache", "bus unit", -@@ -22,28 +22,34 @@ +@@ -22,28 +22,34 @@ static char *k8bank[] = { "northbridge", "fixed-issue reoder" }; @@ -58,7 +58,7 @@ static char *nbextendederr[] = { "RAM ECC error", "CRC error", -@@ -65,6 +71,46 @@ +@@ -65,6 +71,46 @@ static char *nbextendederr[] = { "L3 Cache Tag Error", "L3 Cache LRU Error" }; @@ -105,7 +105,7 @@ static char *highbits[32] = { [31] = "valid", [30] = "error overflow (multiple errors)", -@@ -100,6 +146,21 @@ +@@ -100,6 +146,21 @@ static char *k8threshold[] = { "Unknown threshold counter", }; @@ -127,7 +127,7 @@ static void decode_k8_generic_errcode(u64 status) { -@@ -245,21 +306,393 @@ +@@ -245,21 +306,393 @@ static decoder_t decoders[] = { [5] = decode_k8_fr_mc, }; @@ -529,7 +529,7 @@ if (num < NELE(k8bank)) s = k8bank[num]; else if (num >= K8_MCE_THRESHOLD_BASE && -@@ -270,13 +703,16 @@ +@@ -270,13 +703,16 @@ char *k8_bank_name(unsigned num) return buf; } @@ -554,10 +554,10 @@ + } + return 1; } -Index: mcelog-1.20/amd.h +Index: mcelog-1.36/amd.h =================================================================== ---- mcelog-1.20.orig/amd.h 2015-06-15 15:16:07.728108543 +0200 -+++ mcelog-1.20/amd.h 2015-06-15 15:16:14.576500082 +0200 +--- mcelog-1.36.orig/amd.h 2016-05-03 17:45:20.791107676 +0200 ++++ mcelog-1.36/amd.h 2016-05-03 17:45:35.943971068 +0200 @@ -1,6 +1,25 @@ +#include <stdbool.h> + @@ -585,7 +585,7 @@ #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */ #define K8_MCE_THRESHOLD_TOP (K8_MCE_THRESHOLD_BASE + 6 * 9) -@@ -10,6 +29,8 @@ +@@ -10,6 +29,8 @@ int mce_filter_k8(struct mce *m); #define K8_MCELOG_THRESHOLD_L3_CACHE (4 * 9 + 2) #define K8_MCELOG_THRESHOLD_FBDIMM (4 * 9 + 3) @@ -594,7 +594,7 @@ #define EC(x) ((x) & 0xffff) #define XEC(x, mask) (((x) >> 16) & mask) -@@ -22,23 +43,20 @@ +@@ -22,23 +43,20 @@ int mce_filter_k8(struct mce *m); #define INT_ERROR(x) (((x) & 0xF4FF) == 0x0400) #define TT(x) (((x) >> 2) & 0x3) @@ -624,7 +624,7 @@ enum tt_ids { TT_INSTR = 0, -@@ -72,3 +90,7 @@ +@@ -72,3 +90,7 @@ enum rrrr_ids { R4_EVICT, R4_SNOOP, }; @@ -632,11 +632,11 @@ +#define CASE_AMD_CPUS \ + case CPU_K8: \ + case CPU_F10H -Index: mcelog-1.20/mcelog.h +Index: mcelog-1.36/mcelog.h =================================================================== ---- mcelog-1.20.orig/mcelog.h 2015-06-15 15:16:07.740109229 +0200 -+++ mcelog-1.20/mcelog.h 2015-06-15 15:16:14.580500307 +0200 -@@ -111,6 +111,7 @@ +--- mcelog-1.36.orig/mcelog.h 2016-05-03 17:45:20.727104029 +0200 ++++ mcelog-1.36/mcelog.h 2016-05-03 17:45:35.943971068 +0200 +@@ -111,6 +111,7 @@ enum cputype { CPU_P6OLD, CPU_CORE2, /* 65nm and 45nm */ CPU_K8, @@ -644,11 +644,11 @@ CPU_P4, CPU_NEHALEM, CPU_DUNNINGTON, -Index: mcelog-1.20/mcelog.c +Index: mcelog-1.36/mcelog.c =================================================================== ---- mcelog-1.20.orig/mcelog.c 2015-06-15 15:16:07.752109915 +0200 -+++ mcelog-1.20/mcelog.c 2015-06-15 15:19:18.771031150 +0200 -@@ -144,19 +144,20 @@ +--- mcelog-1.36.orig/mcelog.c 2016-05-03 17:45:20.771106536 +0200 ++++ mcelog-1.36/mcelog.c 2016-05-03 17:45:35.943971068 +0200 +@@ -145,19 +145,20 @@ static void resolveaddr(unsigned long lo static int mce_filter(struct mce *m, unsigned recordlen) { @@ -673,7 +673,7 @@ } static void print_tsc(int cpunum, __u64 tsc, unsigned long time) -@@ -223,6 +224,7 @@ +@@ -224,6 +225,7 @@ static char *cputype_name[] = { [CPU_P6OLD] = "Intel PPro/P2/P3/old Xeon", [CPU_CORE2] = "Intel Core", /* 65nm and 45nm */ [CPU_K8] = "AMD K8 and derivates", @@ -681,7 +681,7 @@ [CPU_P4] = "Intel P4", [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")", [CPU_DUNNINGTON] = "Intel Xeon 7400 series", -@@ -245,6 +247,7 @@ +@@ -250,6 +252,7 @@ static struct config_choice cpu_choices[ { "p6old", CPU_P6OLD }, { "core2", CPU_CORE2 }, { "k8", CPU_K8 }, @@ -689,7 +689,7 @@ { "p4", CPU_P4 }, { "dunnington", CPU_DUNNINGTON }, { "xeon74xx", CPU_DUNNINGTON }, -@@ -343,15 +346,13 @@ +@@ -354,15 +357,13 @@ static enum cputype setup_cpuid(u32 cpuv parse_cpuid(cpuid, &family, &model); @@ -708,7 +708,7 @@ cpuvendor, family, model); return CPU_GENERIC; } -@@ -526,14 +527,9 @@ +@@ -539,14 +540,9 @@ int is_cpu_supported(void) } if (seen == ALL) { ++++++ add-f11h-support.patch ++++++ --- /var/tmp/diff_new_pack.mi1bOK/_old 2016-05-11 16:37:17.000000000 +0200 +++ /var/tmp/diff_new_pack.mi1bOK/_new 2016-05-11 16:37:17.000000000 +0200 @@ -1,10 +1,10 @@ Add F11h decoding support Signed-off-by: Borislav Petkov <[email protected]> -Index: mcelog-1.0.1/amd.c +Index: mcelog-1.36/amd.c =================================================================== ---- mcelog-1.0.1.orig/amd.c -+++ mcelog-1.0.1/amd.c +--- mcelog-1.36.orig/amd.c 2016-05-03 17:45:35.943971068 +0200 ++++ mcelog-1.36/amd.c 2016-05-03 17:45:39.500173684 +0200 @@ -155,6 +155,8 @@ enum cputype select_amd_cputype(u32 fami return CPU_K8; case 0x10: @@ -54,10 +54,10 @@ default: Eprintf("Huh? What family is it: 0x%x?!\n", cpu); return; -Index: mcelog-1.0.1/amd.h +Index: mcelog-1.36/amd.h =================================================================== ---- mcelog-1.0.1.orig/amd.h -+++ mcelog-1.0.1/amd.h +--- mcelog-1.36.orig/amd.h 2016-05-03 17:45:35.943971068 +0200 ++++ mcelog-1.36/amd.h 2016-05-03 17:45:39.500173684 +0200 @@ -93,4 +93,5 @@ enum rrrr_ids { #define CASE_AMD_CPUS \ @@ -65,11 +65,11 @@ - case CPU_F10H + case CPU_F10H: \ + case CPU_F11H -Index: mcelog-1.0.1/mcelog.h +Index: mcelog-1.36/mcelog.h =================================================================== ---- mcelog-1.0.1.orig/mcelog.h -+++ mcelog-1.0.1/mcelog.h -@@ -108,6 +108,7 @@ enum cputype { +--- mcelog-1.36.orig/mcelog.h 2016-05-03 17:45:35.943971068 +0200 ++++ mcelog-1.36/mcelog.h 2016-05-03 17:45:39.500173684 +0200 +@@ -112,6 +112,7 @@ enum cputype { CPU_CORE2, /* 65nm and 45nm */ CPU_K8, CPU_F10H, @@ -77,11 +77,11 @@ CPU_P4, CPU_NEHALEM, CPU_DUNNINGTON, -Index: mcelog-1.0.1/mcelog.c +Index: mcelog-1.36/mcelog.c =================================================================== ---- mcelog-1.0.1.orig/mcelog.c -+++ mcelog-1.0.1/mcelog.c -@@ -223,6 +223,7 @@ static char *cputype_name[] = { +--- mcelog-1.36.orig/mcelog.c 2016-05-03 17:45:35.943971068 +0200 ++++ mcelog-1.36/mcelog.c 2016-05-03 17:45:39.500173684 +0200 +@@ -226,6 +226,7 @@ static char *cputype_name[] = { [CPU_CORE2] = "Intel Core", /* 65nm and 45nm */ [CPU_K8] = "AMD K8 and derivates", [CPU_F10H] = "AMD Greyhound", @@ -89,7 +89,7 @@ [CPU_P4] = "Intel P4", [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")", [CPU_DUNNINGTON] = "Intel Xeon 7400 series", -@@ -242,6 +243,7 @@ static struct config_choice cpu_choices[ +@@ -253,6 +254,7 @@ static struct config_choice cpu_choices[ { "core2", CPU_CORE2 }, { "k8", CPU_K8 }, { "f10h", CPU_F10H }, ++++++ add-f12h-support.patch ++++++ --- /var/tmp/diff_new_pack.mi1bOK/_old 2016-05-11 16:37:17.000000000 +0200 +++ /var/tmp/diff_new_pack.mi1bOK/_new 2016-05-11 16:37:17.000000000 +0200 @@ -1,10 +1,10 @@ Add F12h decoding support Signed-off-by: Borislav Petkov <[email protected]> -Index: mcelog-1.0.1/amd.c +Index: mcelog-1.36/amd.c =================================================================== ---- mcelog-1.0.1.orig/amd.c -+++ mcelog-1.0.1/amd.c +--- mcelog-1.36.orig/amd.c 2016-05-03 17:45:39.500173684 +0200 ++++ mcelog-1.36/amd.c 2016-05-03 17:45:41.996315929 +0200 @@ -157,6 +157,8 @@ enum cputype select_amd_cputype(u32 fami return CPU_F10H; case 0x11: @@ -37,10 +37,10 @@ default: Eprintf("Huh? What family is it: 0x%x?!\n", cpu); return; -Index: mcelog-1.0.1/amd.h +Index: mcelog-1.36/amd.h =================================================================== ---- mcelog-1.0.1.orig/amd.h -+++ mcelog-1.0.1/amd.h +--- mcelog-1.36.orig/amd.h 2016-05-03 17:45:39.500173684 +0200 ++++ mcelog-1.36/amd.h 2016-05-03 17:45:41.996315929 +0200 @@ -9,6 +9,7 @@ enum amdcpu { AMD_K8 = 0, AMD_F10H, @@ -56,11 +56,11 @@ - case CPU_F11H + case CPU_F11H: \ + case CPU_F12H -Index: mcelog-1.0.1/mcelog.h +Index: mcelog-1.36/mcelog.h =================================================================== ---- mcelog-1.0.1.orig/mcelog.h -+++ mcelog-1.0.1/mcelog.h -@@ -109,6 +109,7 @@ enum cputype { +--- mcelog-1.36.orig/mcelog.h 2016-05-03 17:45:39.500173684 +0200 ++++ mcelog-1.36/mcelog.h 2016-05-03 17:45:41.996315929 +0200 +@@ -113,6 +113,7 @@ enum cputype { CPU_K8, CPU_F10H, CPU_F11H, @@ -68,11 +68,11 @@ CPU_P4, CPU_NEHALEM, CPU_DUNNINGTON, -Index: mcelog-1.0.1/mcelog.c +Index: mcelog-1.36/mcelog.c =================================================================== ---- mcelog-1.0.1.orig/mcelog.c -+++ mcelog-1.0.1/mcelog.c -@@ -224,6 +224,7 @@ static char *cputype_name[] = { +--- mcelog-1.36.orig/mcelog.c 2016-05-03 17:45:39.500173684 +0200 ++++ mcelog-1.36/mcelog.c 2016-05-03 17:45:41.996315929 +0200 +@@ -227,6 +227,7 @@ static char *cputype_name[] = { [CPU_K8] = "AMD K8 and derivates", [CPU_F10H] = "AMD Greyhound", [CPU_F11H] = "AMD Griffin", @@ -80,7 +80,7 @@ [CPU_P4] = "Intel P4", [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")", [CPU_DUNNINGTON] = "Intel Xeon 7400 series", -@@ -244,6 +245,7 @@ static struct config_choice cpu_choices[ +@@ -255,6 +256,7 @@ static struct config_choice cpu_choices[ { "k8", CPU_K8 }, { "f10h", CPU_F10H }, { "f11h", CPU_F11H }, ++++++ add-f14h-support.patch ++++++ --- /var/tmp/diff_new_pack.mi1bOK/_old 2016-05-11 16:37:17.000000000 +0200 +++ /var/tmp/diff_new_pack.mi1bOK/_new 2016-05-11 16:37:17.000000000 +0200 @@ -1,10 +1,10 @@ Add F14h decoding support Signed-off-by: Borislav Petkov <[email protected]> -Index: mcelog-1.0.1/amd.c +Index: mcelog-1.36/amd.c =================================================================== ---- mcelog-1.0.1.orig/amd.c -+++ mcelog-1.0.1/amd.c +--- mcelog-1.36.orig/amd.c 2016-05-03 17:45:41.996315929 +0200 ++++ mcelog-1.36/amd.c 2016-05-03 17:45:43.452398891 +0200 @@ -159,6 +159,8 @@ enum cputype select_amd_cputype(u32 fami return CPU_F11H; case 0x12: @@ -128,11 +128,11 @@ default: Eprintf("Huh? What family is it: 0x%x?!\n", cpu); return; -Index: mcelog-1.0.1/mcelog.h +Index: mcelog-1.36/mcelog.h =================================================================== ---- mcelog-1.0.1.orig/mcelog.h -+++ mcelog-1.0.1/mcelog.h -@@ -110,6 +110,7 @@ enum cputype { +--- mcelog-1.36.orig/mcelog.h 2016-05-03 17:45:41.996315929 +0200 ++++ mcelog-1.36/mcelog.h 2016-05-03 17:45:43.452398891 +0200 +@@ -114,6 +114,7 @@ enum cputype { CPU_F10H, CPU_F11H, CPU_F12H, @@ -140,10 +140,10 @@ CPU_P4, CPU_NEHALEM, CPU_DUNNINGTON, -Index: mcelog-1.0.1/amd.h +Index: mcelog-1.36/amd.h =================================================================== ---- mcelog-1.0.1.orig/amd.h -+++ mcelog-1.0.1/amd.h +--- mcelog-1.36.orig/amd.h 2016-05-03 17:45:41.996315929 +0200 ++++ mcelog-1.36/amd.h 2016-05-03 17:45:43.452398891 +0200 @@ -96,4 +96,5 @@ enum rrrr_ids { case CPU_K8: \ case CPU_F10H: \ @@ -151,11 +151,11 @@ - case CPU_F12H + case CPU_F12H: \ + case CPU_F14H -Index: mcelog-1.0.1/mcelog.c +Index: mcelog-1.36/mcelog.c =================================================================== ---- mcelog-1.0.1.orig/mcelog.c -+++ mcelog-1.0.1/mcelog.c -@@ -225,6 +225,7 @@ static char *cputype_name[] = { +--- mcelog-1.36.orig/mcelog.c 2016-05-03 17:45:41.996315929 +0200 ++++ mcelog-1.36/mcelog.c 2016-05-03 17:45:43.456399118 +0200 +@@ -228,6 +228,7 @@ static char *cputype_name[] = { [CPU_F10H] = "AMD Greyhound", [CPU_F11H] = "AMD Griffin", [CPU_F12H] = "AMD Llano", @@ -163,7 +163,7 @@ [CPU_P4] = "Intel P4", [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")", [CPU_DUNNINGTON] = "Intel Xeon 7400 series", -@@ -246,6 +247,7 @@ static struct config_choice cpu_choices[ +@@ -257,6 +258,7 @@ static struct config_choice cpu_choices[ { "f10h", CPU_F10H }, { "f11h", CPU_F11H }, { "f12h", CPU_F12H }, ++++++ add-f15h-support.patch ++++++ --- /var/tmp/diff_new_pack.mi1bOK/_old 2016-05-11 16:37:17.000000000 +0200 +++ /var/tmp/diff_new_pack.mi1bOK/_new 2016-05-11 16:37:17.000000000 +0200 @@ -1,10 +1,10 @@ Add F15h decoding support Signed-off-by: Borislav Petkov <[email protected]> -Index: mcelog-1.0.1/amd.c +Index: mcelog-1.36/amd.c =================================================================== ---- mcelog-1.0.1.orig/amd.c -+++ mcelog-1.0.1/amd.c +--- mcelog-1.36.orig/amd.c 2016-05-03 17:45:43.452398891 +0200 ++++ mcelog-1.36/amd.c 2016-05-03 17:45:45.316505087 +0200 @@ -72,6 +72,43 @@ static char *nbextendederr[] = { "L3 Cache LRU Error" }; @@ -214,11 +214,11 @@ default: Eprintf("Huh? What family is it: 0x%x?!\n", cpu); return; -Index: mcelog-1.0.1/mcelog.h +Index: mcelog-1.36/mcelog.h =================================================================== ---- mcelog-1.0.1.orig/mcelog.h -+++ mcelog-1.0.1/mcelog.h -@@ -111,6 +111,7 @@ enum cputype { +--- mcelog-1.36.orig/mcelog.h 2016-05-03 17:45:43.452398891 +0200 ++++ mcelog-1.36/mcelog.h 2016-05-03 17:45:45.316505087 +0200 +@@ -115,6 +115,7 @@ enum cputype { CPU_F11H, CPU_F12H, CPU_F14H, @@ -226,10 +226,10 @@ CPU_P4, CPU_NEHALEM, CPU_DUNNINGTON, -Index: mcelog-1.0.1/amd.h +Index: mcelog-1.36/amd.h =================================================================== ---- mcelog-1.0.1.orig/amd.h -+++ mcelog-1.0.1/amd.h +--- mcelog-1.36.orig/amd.h 2016-05-03 17:45:43.452398891 +0200 ++++ mcelog-1.36/amd.h 2016-05-03 17:45:45.316505087 +0200 @@ -97,4 +97,5 @@ enum rrrr_ids { case CPU_F10H: \ case CPU_F11H: \ @@ -237,11 +237,11 @@ - case CPU_F14H + case CPU_F14H: \ + case CPU_F15H -Index: mcelog-1.0.1/mcelog.c +Index: mcelog-1.36/mcelog.c =================================================================== ---- mcelog-1.0.1.orig/mcelog.c -+++ mcelog-1.0.1/mcelog.c -@@ -226,6 +226,7 @@ static char *cputype_name[] = { +--- mcelog-1.36.orig/mcelog.c 2016-05-03 17:45:43.456399118 +0200 ++++ mcelog-1.36/mcelog.c 2016-05-03 17:45:45.320505319 +0200 +@@ -229,6 +229,7 @@ static char *cputype_name[] = { [CPU_F11H] = "AMD Griffin", [CPU_F12H] = "AMD Llano", [CPU_F14H] = "AMD Bobcat", @@ -249,7 +249,7 @@ [CPU_P4] = "Intel P4", [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")", [CPU_DUNNINGTON] = "Intel Xeon 7400 series", -@@ -248,6 +249,7 @@ static struct config_choice cpu_choices[ +@@ -259,6 +260,7 @@ static struct config_choice cpu_choices[ { "f11h", CPU_F11H }, { "f12h", CPU_F12H }, { "f14h", CPU_F14H }, ++++++ add-f16h-support.patch ++++++ --- /var/tmp/diff_new_pack.mi1bOK/_old 2016-05-11 16:37:17.000000000 +0200 +++ /var/tmp/diff_new_pack.mi1bOK/_new 2016-05-11 16:37:17.000000000 +0200 @@ -1,10 +1,10 @@ Add F16h decoding support Signed-off-by: Borislav Petkov <[email protected]> -Index: mcelog-1.0.1/amd.c +Index: mcelog-1.36/amd.c =================================================================== ---- mcelog-1.0.1.orig/amd.c -+++ mcelog-1.0.1/amd.c +--- mcelog-1.36.orig/amd.c 2016-05-03 17:45:45.316505087 +0200 ++++ mcelog-1.36/amd.c 2016-05-03 17:45:47.828648285 +0200 @@ -200,6 +200,8 @@ enum cputype select_amd_cputype(u32 fami return CPU_F14H; case 0x15: @@ -86,11 +86,11 @@ default: Eprintf("Huh? What family is it: 0x%x?!\n", cpu); return; -Index: mcelog-1.0.1/mcelog.h +Index: mcelog-1.36/mcelog.h =================================================================== ---- mcelog-1.0.1.orig/mcelog.h -+++ mcelog-1.0.1/mcelog.h -@@ -112,6 +112,7 @@ enum cputype { +--- mcelog-1.36.orig/mcelog.h 2016-05-03 17:45:45.316505087 +0200 ++++ mcelog-1.36/mcelog.h 2016-05-03 17:45:47.828648285 +0200 +@@ -116,6 +116,7 @@ enum cputype { CPU_F12H, CPU_F14H, CPU_F15H, @@ -98,10 +98,10 @@ CPU_P4, CPU_NEHALEM, CPU_DUNNINGTON, -Index: mcelog-1.0.1/amd.h +Index: mcelog-1.36/amd.h =================================================================== ---- mcelog-1.0.1.orig/amd.h -+++ mcelog-1.0.1/amd.h +--- mcelog-1.36.orig/amd.h 2016-05-03 17:45:45.316505087 +0200 ++++ mcelog-1.36/amd.h 2016-05-03 17:45:47.832648501 +0200 @@ -98,4 +98,5 @@ enum rrrr_ids { case CPU_F11H: \ case CPU_F12H: \ @@ -109,11 +109,11 @@ - case CPU_F15H + case CPU_F15H: \ + case CPU_F16H -Index: mcelog-1.0.1/mcelog.c +Index: mcelog-1.36/mcelog.c =================================================================== ---- mcelog-1.0.1.orig/mcelog.c -+++ mcelog-1.0.1/mcelog.c -@@ -227,6 +227,7 @@ static char *cputype_name[] = { +--- mcelog-1.36.orig/mcelog.c 2016-05-03 17:45:45.320505319 +0200 ++++ mcelog-1.36/mcelog.c 2016-05-03 17:45:47.832648501 +0200 +@@ -230,6 +230,7 @@ static char *cputype_name[] = { [CPU_F12H] = "AMD Llano", [CPU_F14H] = "AMD Bobcat", [CPU_F15H] = "AMD Bulldozer", @@ -121,7 +121,7 @@ [CPU_P4] = "Intel P4", [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")", [CPU_DUNNINGTON] = "Intel Xeon 7400 series", -@@ -250,6 +251,7 @@ static struct config_choice cpu_choices[ +@@ -261,6 +262,7 @@ static struct config_choice cpu_choices[ { "f12h", CPU_F12H }, { "f14h", CPU_F14H }, { "f15h", CPU_F15H }, ++++++ email.patch ++++++ --- /var/tmp/diff_new_pack.mi1bOK/_old 2016-05-11 16:37:17.000000000 +0200 +++ /var/tmp/diff_new_pack.mi1bOK/_new 2016-05-11 16:37:17.000000000 +0200 @@ -7,18 +7,18 @@ msg.c | 8 ++ 6 files changed, 343 insertions(+), 2 deletions(-) -Index: mcelog-1.29/Makefile +Index: mcelog-1.36/Makefile =================================================================== ---- mcelog-1.29.orig/Makefile 2016-01-20 18:33:20.000000000 +0100 -+++ mcelog-1.29/Makefile 2016-02-01 17:35:54.959649090 +0100 +--- mcelog-1.36.orig/Makefile 2016-04-15 22:19:32.000000000 +0200 ++++ mcelog-1.36/Makefile 2016-05-03 17:43:23.544426782 +0200 @@ -1,3 +1,4 @@ +CONFIG_EMAIL := 1 CFLAGS := -g -Os prefix := /usr etcprefix := @@ -40,8 +41,9 @@ OBJ := p4.o k8.o mcelog.o dmi.o tsc.o co - broadwell_de.o broadwell_epex.o msr.o bus.o \ - unknown.o + broadwell_de.o broadwell_epex.o skylake_xeon.o \ + msr.o bus.o unknown.o DISKDB_OBJ := diskdb.o dimm.o db.o +EMAIL_OBJ := email.o CLEAN := mcelog dmi tsc dbquery .depend .depend.X dbquery.o ${DISKDB_OBJ} \ @@ -40,10 +40,10 @@ SRC := $(OBJ:.o=.c) mcelog: ${OBJ} version.o -Index: mcelog-1.29/email.c +Index: mcelog-1.36/email.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ mcelog-1.29/email.c 2016-02-01 17:33:02.709891934 +0100 ++++ mcelog-1.36/email.c 2016-05-03 17:43:23.548427010 +0200 @@ -0,0 +1,200 @@ +#include <unistd.h> +#include <signal.h> @@ -245,10 +245,10 @@ + smtp_destroy_session (session); + return 0; +} -Index: mcelog-1.29/email.h +Index: mcelog-1.36/email.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ mcelog-1.29/email.h 2016-02-01 17:33:02.709891934 +0100 ++++ mcelog-1.36/email.h 2016-05-03 17:43:23.548427010 +0200 @@ -0,0 +1,34 @@ +#ifndef _MCELOG_EMAIL_H_ +#define _MCELOG_EMAIL_H_ @@ -284,10 +284,10 @@ +#endif + +#endif -Index: mcelog-1.29/mcelog.c +Index: mcelog-1.36/mcelog.c =================================================================== ---- mcelog-1.29.orig/mcelog.c 2016-01-20 18:33:20.000000000 +0100 -+++ mcelog-1.29/mcelog.c 2016-02-01 17:35:10.417125475 +0100 +--- mcelog-1.36.orig/mcelog.c 2016-04-15 22:19:32.000000000 +0200 ++++ mcelog-1.36/mcelog.c 2016-05-03 17:43:23.548427010 +0200 @@ -37,6 +37,7 @@ #include <assert.h> #include <signal.h> @@ -315,7 +315,7 @@ static char *inputfile; char *processor_flags; static int foreground; -@@ -973,6 +977,7 @@ void usage(void) +@@ -976,6 +980,7 @@ void usage(void) "--no-imc-log Disable extended iMC logging\n" "--is-cpu-supported Exit with return code indicating whether the CPU is supported\n" ); @@ -323,7 +323,7 @@ diskdb_usage(); printf("\n"); print_cputypes(); -@@ -1043,6 +1048,7 @@ static struct option options[] = { +@@ -1046,6 +1051,7 @@ static struct option options[] = { { "no-imc-log", 0, NULL, O_NO_IMC_LOG }, { "is-cpu-supported", 0, NULL, O_IS_CPU_SUPPORTED }, DISKDB_OPTIONS @@ -331,7 +331,7 @@ {} }; -@@ -1223,11 +1229,86 @@ static void drop_cred(void) +@@ -1226,11 +1232,86 @@ static void drop_cred(void) } } @@ -418,7 +418,7 @@ if (recordlen == 0) { Wprintf("no data in mce record\n"); -@@ -1254,12 +1335,16 @@ static void process(int fd, unsigned rec +@@ -1257,12 +1338,16 @@ static void process(int fd, unsigned rec finish = 1; if (!mce_filter(mce, recordlen)) continue; @@ -435,7 +435,7 @@ flushlog(); } -@@ -1370,6 +1455,8 @@ int main(int ac, char **av) +@@ -1373,6 +1458,8 @@ int main(int ac, char **av) exit(0); } else if (diskdb_cmd(opt, ac, av)) { exit(0); @@ -444,7 +444,7 @@ } else if (opt == 0) break; } -@@ -1402,6 +1489,10 @@ int main(int ac, char **av) +@@ -1405,6 +1492,10 @@ int main(int ac, char **av) logfn = av[optind++]; if (av[optind]) usage(); @@ -455,11 +455,11 @@ checkdmi(); general_setup(); -Index: mcelog-1.29/mcelog.h +Index: mcelog-1.36/mcelog.h =================================================================== ---- mcelog-1.29.orig/mcelog.h 2016-01-20 18:33:20.000000000 +0100 -+++ mcelog-1.29/mcelog.h 2016-02-01 17:35:07.072936045 +0100 -@@ -134,6 +134,7 @@ enum cputype { +--- mcelog-1.36.orig/mcelog.h 2016-04-15 22:19:32.000000000 +0200 ++++ mcelog-1.36/mcelog.h 2016-05-03 17:43:23.548427010 +0200 +@@ -135,6 +135,7 @@ enum cputype { enum option_ranges { O_COMMON = 500, O_DISKDB = 1000, @@ -467,10 +467,10 @@ }; enum syslog_opt { -Index: mcelog-1.29/msg.c +Index: mcelog-1.36/msg.c =================================================================== ---- mcelog-1.29.orig/msg.c 2016-01-20 18:33:20.000000000 +0100 -+++ mcelog-1.29/msg.c 2016-02-01 17:33:02.713892160 +0100 +--- mcelog-1.36.orig/msg.c 2016-04-15 22:19:32.000000000 +0200 ++++ mcelog-1.36/msg.c 2016-05-03 17:43:23.548427010 +0200 @@ -8,10 +8,13 @@ #include "mcelog.h" #include "msg.h" ++++++ fix_setgroups_missing_call.patch ++++++ --- /var/tmp/diff_new_pack.mi1bOK/_old 2016-05-11 16:37:17.000000000 +0200 +++ /var/tmp/diff_new_pack.mi1bOK/_new 2016-05-11 16:37:17.000000000 +0200 @@ -1,7 +1,7 @@ -Index: mcelog-1.0.8/mcelog.c +Index: mcelog-1.36/mcelog.c =================================================================== ---- mcelog-1.0.8.orig/mcelog.c 2015-01-22 14:56:56.151710136 +0100 -+++ mcelog-1.0.8/mcelog.c 2015-01-23 09:58:35.252799171 +0100 +--- mcelog-1.36.orig/mcelog.c 2016-05-03 17:45:47.832648501 +0200 ++++ mcelog-1.36/mcelog.c 2016-05-03 17:45:53.348962792 +0200 @@ -37,6 +37,7 @@ #include <assert.h> #include <signal.h> @@ -10,7 +10,7 @@ #include <sys/wait.h> #include <fnmatch.h> #include "mcelog.h" -@@ -1185,6 +1186,14 @@ +@@ -1223,6 +1224,14 @@ static void general_setup(void) static void drop_cred(void) { ++++++ mcelog-1.29.tar.bz2 -> mcelog-1.36.tar.bz2 ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/Makefile new/mcelog-1.36/Makefile --- old/mcelog-1.29/Makefile 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/Makefile 2016-04-15 22:19:32.000000000 +0200 @@ -37,8 +37,8 @@ eventloop.o leaky-bucket.o memdb.o server.o trigger.o \ client.o cache.o sysfs.o yellow.o page.o rbtree.o \ xeon75xx.o sandy-bridge.o ivy-bridge.o haswell.o \ - broadwell_de.o broadwell_epex.o msr.o bus.o \ - unknown.o + broadwell_de.o broadwell_epex.o skylake_xeon.o \ + msr.o bus.o unknown.o DISKDB_OBJ := diskdb.o dimm.o db.o CLEAN := mcelog dmi tsc dbquery .depend .depend.X dbquery.o ${DISKDB_OBJ} \ version.o version.c version.tmp diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/bitfield.c new/mcelog-1.36/bitfield.c --- old/mcelog-1.29/bitfield.c 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/bitfield.c 2016-04-15 22:19:32.000000000 +0200 @@ -56,7 +56,7 @@ u64 v = (status >> f->start) & mask; if (v > 0 || f->force) { char fmt[30]; - snprintf(fmt, 30, "%%s: %s\n", f->fmt ? f->fmt : "%Lu"); + snprintf(fmt, 30, "%%s: %s\n", f->fmt ? f->fmt : "%llu"); Wprintf(fmt, f->name, v); } } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/bitfield.h new/mcelog-1.36/bitfield.h --- old/mcelog-1.29/bitfield.h 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/bitfield.h 2016-04-15 22:19:32.000000000 +0200 @@ -16,10 +16,10 @@ #define FIELD(start_bit, name) { start_bit, name, NELE(name) } #define SBITFIELD(start_bit, string) { start_bit, ((char * [2]) { NULL, string }), 2 } -#define NUMBER(start, end, name) { start, end, name, "%Lu", 0 } -#define NUMBERFORCE(start, end, name) { start, end, name, "%Lu", 1 } -#define HEXNUMBER(start, end, name) { start, end, name, "%Lx", 0 } -#define HEXNUMBERFORCE(start, end, name) { start, end, name, "%Lx", 1 } +#define NUMBER(start, end, name) { start, end, name, "%llu", 0 } +#define NUMBERFORCE(start, end, name) { start, end, name, "%llu", 1 } +#define HEXNUMBER(start, end, name) { start, end, name, "%llx", 0 } +#define HEXNUMBERFORCE(start, end, name) { start, end, name, "%llx", 1 } void decode_bitfield(u64 status, struct field *fields); void decode_numfield(u64 status, struct numfield *fields); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/broadwell_epex.c new/mcelog-1.36/broadwell_epex.c --- old/mcelog-1.29/broadwell_epex.c 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/broadwell_epex.c 2016-04-15 22:19:32.000000000 +0200 @@ -91,7 +91,7 @@ [0x22] = "Phy detected in-band reset (no width change)", [0x23] = "Link failover clock failover", [0x30] = "Rx detected CRC error - successful LLR after Phy re-init", - [0x31] = "Rx detected CRC error - successful LLR wihout Phy re-init", + [0x31] = "Rx detected CRC error - successful LLR without Phy re-init", }; static struct field qpi_mc[] = { diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/core2.c new/mcelog-1.36/core2.c --- old/mcelog-1.29/core2.c 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/core2.c 2016-04-15 22:19:32.000000000 +0200 @@ -69,7 +69,7 @@ FIELD(31, reserved_1bit), FIELD(32, reserved_3bits), SBITFIELD(35, "BINIT received from external bus"), - SBITFIELD(37, "Received hard error reponse on split transaction (Bus BINIT)"), + SBITFIELD(37, "Received hard error response on split transaction (Bus BINIT)"), {} }; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/dimm.c new/mcelog-1.36/dimm.c --- old/mcelog-1.29/dimm.c 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/dimm.c 2016-04-15 22:19:32.000000000 +0200 @@ -358,7 +358,7 @@ devs = dmi_find_addr(addr); if (devs[0] == NULL) { - Wprintf("No memory found for address %Lx\n", addr); + Wprintf("No memory found for address %llx\n", addr); exit(1); } for (i = 0; devs[i]; i++) { @@ -366,7 +366,7 @@ char *loc = dmi_getstring(&d->header, d->device_locator); struct group *g = find_entry(dimm_db, NULL, "Locator", loc); if (!g) { // shouldn't happen - Eprintf("No record found for %Lx\n", addr); + Eprintf("No record found for %llx\n", addr); return; } unsigned long val = inc_val(g, "corrected errors"); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/dmi.c new/mcelog-1.36/dmi.c --- old/mcelog-1.29/dmi.c 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/dmi.c 2016-04-15 22:19:32.000000000 +0200 @@ -1,6 +1,8 @@ /* Copyright (C) 2006 Andi Kleen, SuSE Labs. + Portions Copyright (C) 2016 Sergio Gelato. + Use SMBIOS/DMI to map address to DIMM description. - For reference see the SMBIOS specification 2.4 + For reference see the SMBIOS specification 2.4, 3.0 dmi is free software; you can redistribute it and/or modify it under the terms of the GNU General Public @@ -55,9 +57,9 @@ } __attribute__((packed)); static struct dmi_entry *entries; -static int entrieslen; +static size_t entrieslen; static int numentries; -static int dmi_length; +static size_t dmi_length; static struct dmi_entry **handle_to_entry; struct dmi_memdev **dmi_dimms; @@ -137,6 +139,59 @@ } } +static int append_sysfs_dmi_entry(unsigned char type, int instance) +{ + char filename[64]; /* 40 bytes should be enough */ + char buf[1024]; + int r; + ssize_t nr; + size_t l; + int fd; + r = snprintf(filename, sizeof(filename), + "/sys/firmware/dmi/entries/%hhu-%d/raw", + type, instance); + if (r < 0 || (unsigned int)r >= sizeof(filename)) { + Eprintf("Can't build pathname for DMI type %hhu instance %d\n", + type, instance); + return 0; + } + fd = open(filename, O_RDONLY); + if (fd == (-1)) { + if (errno != ENOENT) + perror(filename); + return 0; + } + l = dmi_length; + for (;;) { + nr = read(fd, buf, sizeof(buf)); + if (nr < 0) { + if (errno == EINTR) + continue; + perror(filename); + close(fd); + return 0; + } else if (nr > 0) { + while (l + nr > entrieslen) { + entrieslen += 4096; + entries = xrealloc(entries, entrieslen); + } + memcpy((char *)entries+l, buf, nr); + l += nr; + } else { + numentries ++; + dmi_length = l; + close(fd); + return 1; + } + } +} + +static void append_sysfs_dmi_entries(unsigned char type) +{ + int i; + for (i=0; append_sysfs_dmi_entry(type, i); i++) ; +} + static int get_efi_base_addr(size_t *address) { FILE *efi_systab; @@ -190,10 +245,12 @@ int opendmi(void) { struct anchor *a, *abase; + void *ebase; void *p, *q; int pagesize = getpagesize(); int memfd; - unsigned corr; + off_t emapbase, corr; + size_t emapsize; int err = -1; const int segsize = 0x10000; size_t entry_point_addr = 0; @@ -201,6 +258,18 @@ if (entries) return 0; + + if (access("/sys/firmware/dmi/entries/0-0/raw", R_OK) == 0) { + numentries = 0; + append_sysfs_dmi_entries(DMI_MEMORY_ARRAY); + append_sysfs_dmi_entries(DMI_MEMORY_DEVICE); + append_sysfs_dmi_entries(DMI_MEMORY_ARRAY_ADDR); + append_sysfs_dmi_entries(DMI_MEMORY_MAPPED_ADDR); + fill_handles(); + collect_dmi_dimms(); + return 0; + } + memfd = open("/dev/mem", O_RDONLY); if (memfd < 0) { Eprintf("Cannot open /dev/mem for DMI decoding: %s", @@ -262,18 +331,18 @@ if (verbose) printf("DMI tables at %x, %u bytes, %u entries\n", a->table, a->length, a->numentries); - corr = a->table - round_down(a->table, pagesize); - entrieslen = round_up(a->table + a->length, pagesize) - - round_down(a->table, pagesize); - entries = mmap(NULL, entrieslen, - PROT_READ, MAP_SHARED, memfd, - round_down(a->table, pagesize)); - if (entries == (struct dmi_entry *)-1) { + emapbase = round_down(a->table, pagesize); + corr = a->table - emapbase; + emapsize = round_up(a->table + a->length, pagesize) - emapbase; + ebase = mmap(NULL, emapsize, PROT_READ, MAP_SHARED, memfd, emapbase); + if (ebase == MAP_FAILED) { Eprintf("Cannot mmap SMBIOS tables at %x", a->table); - entries = NULL; goto out_mmap; } - entries = (struct dmi_entry *)(((char *)entries) + corr); + entrieslen = a->length; + entries = xalloc_nonzero(entrieslen); + memcpy(entries, (char *)ebase+corr, entrieslen); + munmap(ebase, emapsize); numentries = a->numentries; dmi_length = a->length; fill_handles(); @@ -306,13 +375,15 @@ "?", "Other", "Unknown", "SIMM", "SIP", "Chip", "DIP", "ZIP", "Proprietary Card", "DIMM", "TSOP", "Row of chips", "RIMM", - "SODIMM", "SRIMM" + "SODIMM", "SRIMM", "FB-DIMM" }; static char *memory_types[] = { "?", "Other", "Unknown", "DRAM", "EDRAM", "VRAM", "SRAM", "RAM", "ROM", "FLASH", "EEPROM", "FEPROM", "EPROM", "CDRAM", "3DRAM", - "SDRAM", "SGRAM", "RDRAM", "DDR", "DDR2" + "SDRAM", "SGRAM", "RDRAM", "DDR", "DDR2", "DDR2 FB-DIMM", + "Reserved 0x15", "Reserved 0x16", "Reserved 0x17", "DDR3", + "FBD2", "DDR4", "LPDDR", "LPDDR2", "LPDDR3", "LPDDR4" }; #define LOOKUP(array, val, buf) \ @@ -323,7 +394,8 @@ static char *type_details[16] = { "Reserved", "Other", "Unknown", "Fast-paged", "Static Column", "Pseudo static", "RAMBUS", "Synchronous", "CMOS", "EDO", - "Window DRAM", "Cache DRAM", "Non-volatile", "Res13", "Res14", "Res15" + "Window DRAM", "Cache DRAM", "Non-volatile", "Registered", + "Unbuffered", "LRDIMM" }; static void dump_type_details(unsigned short td) @@ -624,11 +696,11 @@ { if (!entries) return; - munmap(entries, entrieslen); - entries = NULL; FREE(dmi_dimms); FREE(dmi_arrays); FREE(dmi_ranges); FREE(dmi_array_ranges); FREE(handle_to_entry); + FREE(entries); + entrieslen = 0; } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/haswell.c new/mcelog-1.36/haswell.c --- old/mcelog-1.29/haswell.c 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/haswell.c 2016-04-15 22:19:32.000000000 +0200 @@ -91,7 +91,7 @@ [0x22] = "Phy detected in-band reset (no width change)", [0x23] = "Link failover clock failover", [0x30] = "Rx detected CRC error - successful LLR after Phy re-init", - [0x31] = "Rx detected CRC error - successful LLR wihout Phy re-init", + [0x31] = "Rx detected CRC error - successful LLR without Phy re-init", }; static struct field qpi_mc[] = { diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/intel.c new/mcelog-1.36/intel.c --- old/mcelog-1.29/intel.c 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/intel.c 2016-04-15 22:19:32.000000000 +0200 @@ -36,7 +36,7 @@ cpu == CPU_IVY_BRIDGE || cpu == CPU_IVY_BRIDGE_EPEX || cpu == CPU_HASWELL || cpu == CPU_HASWELL_EPEX || cpu == CPU_BROADWELL || cpu == CPU_BROADWELL_DE || cpu == CPU_BROADWELL_EPEX || - cpu == CPU_KNIGHTS_LANDING || cpu == CPU_SKYLAKE) + cpu == CPU_KNIGHTS_LANDING || cpu == CPU_SKYLAKE || cpu == CPU_SKYLAKE_XEON) memory_error_support = 1; } @@ -89,6 +89,8 @@ return CPU_ATOM; else if (model == 0x4e || model == 0x5e) return CPU_SKYLAKE; + else if (model == 0x55) + return CPU_SKYLAKE_XEON; if (model > 0x1a) { Eprintf("Family 6 Model %x CPU: only decoding architectural errors\n", model); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/intel.h new/mcelog-1.36/intel.h --- old/mcelog-1.29/intel.h 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/intel.h 2016-04-15 22:19:32.000000000 +0200 @@ -23,6 +23,8 @@ case CPU_BROADWELL: \ case CPU_BROADWELL_DE: \ case CPU_BROADWELL_EPEX: \ + case CPU_ATOM: \ case CPU_KNIGHTS_LANDING: \ - case CPU_SKYLAKE + case CPU_SKYLAKE: \ + case CPU_SKYLAKE_XEON diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/k8.c new/mcelog-1.36/k8.c --- old/mcelog-1.29/k8.c 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/k8.c 2016-04-15 22:19:32.000000000 +0200 @@ -89,7 +89,7 @@ [0] = "err cpu0", }; static char *k8threshold[] = { - [0 ... K8_MCELOG_THRESHOLD_DRAM_ECC - 1] = "Unknow threshold counter", + [0 ... K8_MCELOG_THRESHOLD_DRAM_ECC - 1] = "Unknown threshold counter", [K8_MCELOG_THRESHOLD_DRAM_ECC] = "MC4_MISC0 DRAM threshold", [K8_MCELOG_THRESHOLD_LINK] = "MC4_MISC1 Link threshold", [K8_MCELOG_THRESHOLD_L3_CACHE] = "MC4_MISC2 L3 Cache threshold", diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/mcelog.c new/mcelog-1.36/mcelog.c --- old/mcelog-1.29/mcelog.c 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/mcelog.c 2016-04-15 22:19:32.000000000 +0200 @@ -238,6 +238,7 @@ [CPU_KNIGHTS_LANDING] = "Knights Landing", [CPU_ATOM] = "ATOM", [CPU_SKYLAKE] = "Skylake", + [CPU_SKYLAKE_XEON] = "Skylake server", }; static struct config_choice cpu_choices[] = { @@ -286,6 +287,7 @@ { "xeon-v4", CPU_BROADWELL_EPEX }, { "atom", CPU_ATOM }, { "skylake", CPU_SKYLAKE }, + { "skylake_server", CPU_SKYLAKE_XEON }, { NULL } }; @@ -449,7 +451,8 @@ if (cputype != CPU_SANDY_BRIDGE_EP && cputype != CPU_IVY_BRIDGE_EPEX && cputype != CPU_HASWELL_EPEX && cputype != CPU_BROADWELL && cputype != CPU_BROADWELL_DE && cputype != CPU_BROADWELL_EPEX && - cputype != CPU_KNIGHTS_LANDING && cputype != CPU_SKYLAKE) + cputype != CPU_KNIGHTS_LANDING && cputype != CPU_SKYLAKE && + cputype != CPU_SKYLAKE_XEON) resolveaddr(m->addr); if (!ascii_mode && ismemerr && (m->status & MCI_STATUS_ADDRV)) { diskdb_resolve_addr(m->addr); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/mcelog.conf new/mcelog-1.36/mcelog.conf --- old/mcelog-1.29/mcelog.conf 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/mcelog.conf 2016-04-15 22:19:32.000000000 +0200 @@ -23,7 +23,7 @@ # If this value is set incorrectly the decoded output will be likely incorrect. # By default when this parameter is not set mcelog uses the CPU it is running on # on very new kernels the mcelog events reported by the kernel also carry -# the CPU type which is used too when available and not overriden. +# the CPU type which is used too when available and not overridden. # Enable daemon mode: #daemon = yes @@ -132,7 +132,7 @@ mem-ce-error-threshold = 100 / 24h -# Log socket error threshold explicitely? +# Log socket error threshold explicitly? mem-ce-error-log = yes # Trigger script for uncorrected bus error events @@ -148,7 +148,7 @@ # Processing of cache error thresholds reported by Intel CPUs. cache-threshold-trigger = cache-error-trigger -# Should cache threshold events be logged explicitely? +# Should cache threshold events be logged explicitly? cache-threshold-log = yes [page] @@ -159,7 +159,7 @@ # Trigger script for corrected errors. # memory-ce-trigger = page-error-trigger -# Should page threshold events be logged explicitely? +# Should page threshold events be logged explicitly? memory-ce-log = yes # specify the internal action in mcelog to exceeding a page error threshold diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/mcelog.conf.5 new/mcelog-1.36/mcelog.conf.5 --- old/mcelog-1.29/mcelog.conf.5 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/mcelog.conf.5 2016-04-15 22:19:32.000000000 +0200 @@ -43,7 +43,7 @@ If this value is set incorrectly the decoded output will be likely incorrect. By default when this parameter is not set mcelog uses the CPU it is running on on very new kernels the mcelog events reported by the kernel also carry -the CPU type which is used too when available and not overriden. +the CPU type which is used too when available and not overridden. .PP .PP Enable daemon mode: @@ -204,7 +204,7 @@ .B mem-ce-error-threshold = 100 / 24h .PP .PP - log socket error threshold explicitely? + log socket error threshold explicitly? .PP .B mem-ce-error-log = yes .PP @@ -230,7 +230,7 @@ .B cache-threshold-trigger = cache-error-trigger .PP .PP -Should cache threshold events be logged explicitely? +Should cache threshold events be logged explicitly? .PP .B cache-threshold-log = yes .PP @@ -246,7 +246,7 @@ memory-ce-trigger = page-error-trigger .PP .PP -Should page threshold events be logged explicitely? +Should page threshold events be logged explicitly? .PP .B memory-ce-log = yes .PP diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/mcelog.h new/mcelog-1.36/mcelog.h --- old/mcelog-1.29/mcelog.h 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/mcelog.h 2016-04-15 22:19:32.000000000 +0200 @@ -129,6 +129,7 @@ CPU_KNIGHTS_LANDING, CPU_ATOM, CPU_SKYLAKE, + CPU_SKYLAKE_XEON, }; enum option_ranges { diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/msr.c new/mcelog-1.36/msr.c --- old/mcelog-1.29/msr.c 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/msr.c 2016-04-15 22:19:32.000000000 +0200 @@ -20,27 +20,28 @@ return; default: SYSERRprintf("Cannot open %s to set imc_log\n", fpath); - exit(1); + return; } } if (pread(fd, &data, sizeof data, msr) != sizeof data) { SYSERRprintf("Cannot read MSR_ERROR_CONTROL from %s\n", fpath); - exit(1); + return; } data |= bit; if (pwrite(fd, &data, sizeof data, msr) != sizeof data) { SYSERRprintf("Cannot write MSR_ERROR_CONTROL to %s\n", fpath); - exit(1); + return; } if (pread(fd, &data, sizeof data, msr) != sizeof data) { SYSERRprintf("Cannot re-read MSR_ERROR_CONTROL from %s\n", fpath); - exit(1); + return; } if ((data & bit) == 0) Lprintf("No DIMM detection available on cpu %d (normal in virtual environments)\n", cpu); close(fd); } +/* XXX: assumes all CPUs are already onlined. */ void set_imc_log(int cputype) { int cpu, ncpus = sysconf(_SC_NPROCESSORS_CONF); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/p4.c new/mcelog-1.36/p4.c --- old/mcelog-1.29/p4.c 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/p4.c 2016-04-15 22:19:32.000000000 +0200 @@ -38,6 +38,7 @@ #include "haswell.h" #include "broadwell_de.h" #include "broadwell_epex.h" +#include "skylake_xeon.h" /* decode mce for P4/Xeon and Core2 family */ @@ -424,6 +425,9 @@ case CPU_BROADWELL_EPEX: bdw_epex_decode_model(cputype, log->bank, log->status, log->misc); break; + case CPU_SKYLAKE_XEON: + skylake_s_decode_model(cputype, log->bank, log->status, log->misc); + break; } } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/skylake_xeon.c new/mcelog-1.36/skylake_xeon.c --- old/mcelog-1.29/skylake_xeon.c 1970-01-01 01:00:00.000000000 +0100 +++ new/mcelog-1.36/skylake_xeon.c 2016-04-15 22:19:32.000000000 +0200 @@ -0,0 +1,210 @@ +/* Copyright (C) 2016 Intel Corporation + Decode Intel Skylake specific machine check errors. + + mcelog is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public + License as published by the Free Software Foundation; version + 2. + + mcelog is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should find a copy of v2 of the GNU General Public License somewhere + on your Linux system; if not, write to the Free Software Foundation, + Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + Author: Tony Luck +*/ + +#include "mcelog.h" +#include "bitfield.h" +#include "skylake_xeon.h" +#include "memdb.h" + +/* See IA32 SDM Vol3B Table 16-27 */ + +static char *pcu_1[] = { + [0x00] = "No Error", + [0x0d] = "MCA_DMI_TRAINING_TIMEOUT", + [0x0f] = "MCA_DMI_CPU_RESET_ACK_TIMEOUT", + [0x10] = "MCA_MORE_THAN_ONE_LT_AGENT", + [0x1e] = "MCA_BIOS_RST_CPL_INVALID_SEQ", + [0x1f] = "MCA_BIOS_INVALID_PKG_STATE_CONFIG", + [0x25] = "MCA_MESSAGE_CHANNEL_TIMEOUT", + [0x27] = "MCA_MSGCH_PMREQ_CMP_TIMEOUT", + [0x30] = "MCA_PKGC_DIRECT_WAKE_RING_TIMEOUT", + [0x31] = "MCA_PKGC_INVALID_RSP_PCH", + [0x33] = "MCA_PKGC_WATCHDOG_HANG_CBZ_DOWN", + [0x34] = "MCA_PKGC_WATCHDOG_HANG_CBZ_UP", + [0x38] = "MCA_PKGC_WATCHDOG_HANG_C3_UP_SF", + [0x40] = "MCA_SVID_VCCIN_VR_ICC_MAX_FAILURE", + [0x41] = "MCA_SVID_COMMAND_TIMEOUT", + [0x42] = "MCA_SVID_VCCIN_VR_VOUT_FAILURE", + [0x43] = "MCA_SVID_CPU_VR_CAPABILITY_ERROR", + [0x44] = "MCA_SVID_CRITICAL_VR_FAILED", + [0x45] = "MCA_SVID_SA_ITD_ERROR", + [0x46] = "MCA_SVID_READ_REG_FAILED", + [0x47] = "MCA_SVID_WRITE_REG_FAILED", + [0x48] = "MCA_SVID_PKGC_INIT_FAILED", + [0x49] = "MCA_SVID_PKGC_CONFIG_FAILED", + [0x4a] = "MCA_SVID_PKGC_REQUEST_FAILED", + [0x4b] = "MCA_SVID_IMON_REQUEST_FAILED", + [0x4c] = "MCA_SVID_ALERT_REQUEST_FAILED", + [0x4d] = "MCA_SVID_MCP_VR_ABSENT_OR_RAMP_ERROR", + [0x4e] = "MCA_SVID_UNEXPECTED_MCP_VR_DETECTED", + [0x51] = "MCA_FIVR_CATAS_OVERVOL_FAULT", + [0x52] = "MCA_FIVR_CATAS_OVERCUR_FAULT", + [0x58] = "MCA_WATCHDOG_TIMEOUT_PKGC_SLAVE", + [0x59] = "MCA_WATCHDOG_TIMEOUT_PKGC_MASTER", + [0x5a] = "MCA_WATCHDOG_TIMEOUT_PKGS_MASTER", + [0x61] = "MCA_PKGS_CPD_UNCPD_TIMEOUT", + [0x63] = "MCA_PKGS_INVALID_REQ_PCH", + [0x64] = "MCA_PKGS_INVALID_REQ_INTERNAL", + [0x65] = "MCA_PKGS_INVALID_RSP_INTERNAL", + [0x6b] = "MCA_PKGS_SMBUS_VPP_PAUSE_TIMEOUT", + [0x81] = "MCA_RECOVERABLE_DIE_THERMAL_TOO_HOT", +}; + +static struct field pcu_mc4[] = { + FIELD(24, pcu_1), + {} +}; + +/* See IA32 SDM Vol3B Table 16-28 */ + +static char *qpi[] = { + [0x00] = "UC Phy Initialization Failure", + [0x01] = "UC Phy detected drift buffer alarm", + [0x02] = "UC Phy detected latency buffer rollover", + [0x10] = "UC LL Rx detected CRC error: unsuccessful LLR: entered abort state", + [0x11] = "UC LL Rx unsupported or undefined packet", + [0x12] = "UC LL or Phy control error", + [0x13] = "UC LL Rx parameter exchange exception", + [0x1F] = "UC LL detected control error from the link-mesh interface", + [0x20] = "COR Phy initialization abort", + [0x21] = "COR Phy reset", + [0x22] = "COR Phy lane failure, recovery in x8 width", + [0x23] = "COR Phy L0c error corrected without Phy reset", + [0x24] = "COR Phy L0c error triggering Phy Reset", + [0x25] = "COR Phy L0p exit error corrected with Phy reset", + [0x30] = "COR LL Rx detected CRC error - successful LLR without Phy Reinit", + [0x31] = "COR LL Rx detected CRC error - successful LLR with Phy Reinit", +}; + +static struct field qpi_mc[] = { + FIELD(16, qpi), + {} +}; + +/* These apply to MSCOD 0x12 "UC LL or Phy control error" */ +static struct field qpi_0x12[] = { + SBITFIELD(22, "Phy Control Error"), + SBITFIELD(23, "Unexpected Retry.Ack flit"), + SBITFIELD(24, "Unexpected Retry.Req flit"), + SBITFIELD(25, "RF parity error"), + SBITFIELD(26, "Routeback Table error"), + SBITFIELD(27, "unexpected Tx Protocol flit (EOP, Header or Data)"), + SBITFIELD(28, "Rx Header-or-Credit BGF credit overflow/underflow"), + SBITFIELD(29, "Link Layer Reset still in progress when Phy enters L0"), + SBITFIELD(30, "Link Layer reset initiated while protocol traffic not idle"), + SBITFIELD(31, "Link Layer Tx Parity Error"), + {} +}; + +/* See IA32 SDM Vol3B Table 16-29 */ + +static struct field mc_bits[] = { + SBITFIELD(16, "Address parity error"), + SBITFIELD(17, "HA write data parity error"), + SBITFIELD(18, "HA write byte enable parity error"), + SBITFIELD(19, "Corrected patrol scrub error"), + SBITFIELD(20, "Uncorrected patrol scrub error"), + SBITFIELD(21, "Corrected spare error"), + SBITFIELD(22, "Uncorrected spare error"), + SBITFIELD(23, "Any HA read error"), + SBITFIELD(24, "WDB read parity error"), + SBITFIELD(25, "DDR4 command address parity error"), + SBITFIELD(26, "Uncorrected address parity error"), + {} +}; + +static char *mc_0x8xx[] = { + [0x0] = "Unrecognized request type", + [0x1] = "Read response to an invalid scoreboard entry", + [0x2] = "Unexpected read response", + [0x3] = "DDR4 completion to an invalid scoreboard entry", + [0x4] = "Completion to an invalid scoreboard entry", + [0x5] = "Completion FIFO overflow", + [0x6] = "Correctable parity error", + [0x7] = "Uncorrectable error", + [0x8] = "Interrupt received while outstanding interrupt was not ACKed", + [0x9] = "ERID FIFO overflow", + [0xa] = "Error on Write credits", + [0xb] = "Error on Read credits", + [0xc] = "Scheduler error", + [0xd] = "Error event", +}; + +static struct field memctrl_mc13[] = { + FIELD(16, mc_0x8xx), + {} +}; + +/* See IA32 SDM Vol3B Table 16-30 */ + +static struct field m2m[] = { + SBITFIELD(16, "MscodDataRdErr"), + SBITFIELD(17, "Reserved"), + SBITFIELD(18, "MscodPtlWrErr"), + SBITFIELD(19, "MscodFullWrErr"), + SBITFIELD(20, "MscodBgfErr"), + SBITFIELD(21, "MscodTimeout"), + SBITFIELD(22, "MscodParErr"), + SBITFIELD(23, "MscodBucket1Err"), + {} +}; + +void skylake_s_decode_model(int cputype, int bank, u64 status, u64 misc) +{ + switch (bank) { + case 4: + Wprintf("PCU: "); + switch (EXTRACT(status, 0, 15) & ~(1ull << 12)) { + case 0x402: case 0x403: + Wprintf("Internal errors "); + break; + case 0x406: + Wprintf("Intel TXT errors "); + break; + case 0x407: + Wprintf("Other UBOX Internal errors "); + break; + } + if (EXTRACT(status, 16, 19)) + Wprintf("PCU internal error "); + decode_bitfield(status, pcu_mc4); + break; + case 5: + case 12: + case 19: + Wprintf("QPI: "); + decode_bitfield(status, qpi_mc); + if (EXTRACT(status, 16, 21) == 0x12) + decode_bitfield(status, qpi_0x12); + break; + case 7: case 8: + Wprintf("M2M: "); + decode_bitfield(status, m2m); + break; + case 13: case 14: case 15: + case 16: case 17: case 18: + Wprintf("MemCtrl: "); + if (EXTRACT(status, 27, 27)) + decode_bitfield(status, memctrl_mc13); + else + decode_bitfield(status, mc_bits); + break; + } +} diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/skylake_xeon.h new/mcelog-1.36/skylake_xeon.h --- old/mcelog-1.29/skylake_xeon.h 1970-01-01 01:00:00.000000000 +0100 +++ new/mcelog-1.36/skylake_xeon.h 2016-04-15 22:19:32.000000000 +0200 @@ -0,0 +1 @@ +void skylake_s_decode_model(int cputype, int bank, u64 status, u64 misc); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/trigger.c new/mcelog-1.36/trigger.c --- old/mcelog-1.29/trigger.c 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/trigger.c 2016-04-15 22:19:32.000000000 +0200 @@ -151,14 +151,11 @@ void trigger_wait(void) { - int sig; - sigset_t mask; - sigemptyset(&mask); - sigaddset(&mask, SIGCHLD); - while (num_children > 0) { - if (sigwait(&mask, &sig) < 0) - SYSERRprintf("sigwait waiting for children"); - } + int status; + int pid; + + while ((pid = waitpid((pid_t)-1, &status, 0)) > 0) + finish_child(pid, status); } int trigger_check(char *s) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.29/tsc.c new/mcelog-1.36/tsc.c --- old/mcelog-1.29/tsc.c 2016-01-20 18:33:20.000000000 +0100 +++ new/mcelog-1.36/tsc.c 2016-04-15 22:19:32.000000000 +0200 @@ -161,7 +161,7 @@ { char *buf; u64 tsc = rdtscll(); - printf("%Lx tsc\n", tsc); + printf("%llx tsc\n", tsc); if (decode_tsc_current(&buf, 0, CPU_CORE2, 0.0, tsc) >= 0) printf("%s\n", buf); else ++++++ mcelog.systemd ++++++ --- /var/tmp/diff_new_pack.mi1bOK/_old 2016-05-11 16:37:17.000000000 +0200 +++ /var/tmp/diff_new_pack.mi1bOK/_new 2016-05-11 16:37:17.000000000 +0200 @@ -1,6 +1,7 @@ [Unit] Description=Machine Check Exception Logging Daemon ConditionVirtualization=false +ConditionPathExists=/dev/mcelog [Service] EnvironmentFile=-/etc/sysconfig/mcelog
