Hello community, here is the log from the commit of package cpuid for openSUSE:Factory checked in at 2016-09-07 11:48:21 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/cpuid (Old) and /work/SRC/openSUSE:Factory/.cpuid.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "cpuid" Changes: -------- --- /work/SRC/openSUSE:Factory/cpuid/cpuid.changes 2015-11-18 22:34:35.000000000 +0100 +++ /work/SRC/openSUSE:Factory/.cpuid.new/cpuid.changes 2016-09-07 11:48:24.000000000 +0200 @@ -1,0 +2,17 @@ +Tue Aug 30 08:57:28 UTC 2016 - [email protected] + +- Update to new upstream release 20160814 +* cpuinfo2cpuid: Added a script that takes input from a + /proc/cpuinfo file and converts it into suitable input to + cpuid. The information that cpuid is capable of producing based + on this very limited input information is slight, but + apparently there is interest in getting the synthesized (synth) + leaf from this. +* Support SGX, MPX, BNDLDX/BNDSTX, RDPID, and IA32_XSS PT state. +* Add information for Skylake, Broadwell, Broadwell-E and -EX + processors, Atom C2000 (Avoton) with A0/A1 steppings, Atom + Z3n00 (Bay Trail) stepping 1, Xeon D-1500 (Broadwell-DE) V2 + stepping, corrected Atom Z8000 (Cherry Trail), added Atom S1200 + (Centerton) and VIA Eden. + +------------------------------------------------------------------- Old: ---- cpuid-20151017.src.tar.gz New: ---- cpuid-20160814.src.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ cpuid.spec ++++++ --- /var/tmp/diff_new_pack.2PDzSe/_old 2016-09-07 11:48:25.000000000 +0200 +++ /var/tmp/diff_new_pack.2PDzSe/_new 2016-09-07 11:48:25.000000000 +0200 @@ -2,7 +2,7 @@ # # spec file for package cpuid # -# Copyright (c) 2013 SUSE LINUX Products GmbH, Nuernberg, Germany. +# Copyright (c) 2016 SUSE LINUX GmbH, Nuernberg, Germany. # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -18,19 +18,19 @@ Name: cpuid -Version: 20151017 +Version: 20160814 Release: 0 Summary: x86 CPU identification tool License: GPL-2.0+ Group: System/Management -URL: http://etallen.com/cpuid.html +Url: http://etallen.com/cpuid.html Source: http://etallen.com/cpuid/%name-%version.src.tar.gz -BuildRoot: %_tmppath/%name-%version-build +BuildRoot: %{_tmppath}/%{name}-%{version}-build BuildRequires: gcc BuildRequires: glibc-devel BuildRequires: make -Exclusivearch: %ix86 x86_64 +ExclusiveArch: %ix86 x86_64 %description cpuid executes the CPUID instruction on x86-family CPUs and decodes @@ -48,13 +48,14 @@ make CFLAGS="$CFLAGS" %install -install -Dm 0755 cpuid "%buildroot/%_bindir/cpuid" -install -Dm 0644 cpuid.man "%buildroot/%_mandir/man1/cpuid.1" +mkdir -p "%buildroot/%_bindir" "%buildroot/%_mandir/man1" +install -pm0755 cpuid cpuinfo2cpuid "%buildroot/%_bindir/" +install -pm0644 cpuid.man "%buildroot/%_mandir/man1/cpuid.1" %files %defattr(-,root,root) %doc ChangeLog FUTURE LICENSE -%_bindir/cpuid +%_bindir/cpu* %_mandir/man1/cpuid.1* %changelog ++++++ cpuid-20151017.src.tar.gz -> cpuid-20160814.src.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20151017/ChangeLog new/cpuid-20160814/ChangeLog --- old/cpuid-20151017/ChangeLog 2015-10-17 22:05:16.000000000 +0200 +++ new/cpuid-20160814/ChangeLog 2016-08-15 05:56:19.000000000 +0200 @@ -1,3 +1,84 @@ +Sun Aug 14 2016 Todd Allen <[email protected]> + * Made new release. + * Makefile: Added clean rules to remove tarballs & rpm's with other + version numbers. + +Sun Aug 14 2016 Todd Allen <[email protected]> + * cpuinfo2cpuid: Added a script that takes input from a /proc/cpuinfo + file and converts it into suitable input to cpuid. The information + that cpuid is capable of producing based on this very limited input + information is slight, but apparently there is interest in getting the + synthesized (synth) leaf from this. There isn't much value in using + it with an actual /proc/cpuinfo file on the local system, because just + allowing cpuid to read the local cpuid info will provide better + output. But it could be useful for interpreted saved /proc/cpuinfo + files from another system. I slapped together the basic logic, and + Jirka Hladky turned it into a proper perl script, with actual options, + a help screen, and even documentation. I then made some changes to + give it some more uniform indentation, whitespace, and such. And to + give Jirka Hladky more credit, since his contribution to the script is + larger than my own. + * Makefile: Added rules to generate cpuinfo2cpuid.man from the =pod data + in the script. + * Makefile: Added cpuinfo2cpuid & cpuinfo2cpuid.man to the released + materials. + * cpuid.proto.spec: Added cpuinfo2cpuid & cpuinfo2cpuid.1.gz to released + materials. + +Sun Aug 14 2016 Todd Allen <[email protected]> + * cpuid.c: Changed instances of Kb to KB. In print_2_meaning, changed + an instance of 4k to 4K. + +Sat Aug 13 2016 Todd Allen <[email protected]> + * cpuid.c: Added 7/ebx SGX & FDP_EXCPTN_ONLY flags. + * cpuid.c: Added 7/ecx BNDLDX/BNDSTX MAWAU value field, RDPID & SGX_LC. + * cpuid.c: Added d/0/eax MPX state field. + * cpuid.c: In print_d_0_eax, split MPX and AVX-512 all_or_none fields + into their component parts. Also added IA32_XSS PT state. + * cpuid.c: In print_d_n_ecx, clarify XCR0 as user state and IA32_CXX as + supervisor state. + * cpuid.c: In print_d_n, add MPX and PT features. + * cpuid.c: Renamed leaf 0x10 to Intel's new name. Corrected totally + bogus interpretation of subleaf 0. + * cpuid.c: Generalize subleaf 0x10/1 to also include 0x10/2, and + provide new Intel correct names for each. + * cpuid.c: Added 0x14/0 PTWRITE & power event trace. + * cpuid.c: Added description for leaf 0x12 (SGX Capability) and all its + subleaves. + * cpuid.c: Added descriptionf or leaf 0x17 (SoC vendor) and its + subleaves. + * cpuid.c: Decode new leaf 2 cache descriptors: 0x64 & 0xc4. + * cpuid.c: Updated Atom C2000 (Avoton) with A0/A1 steppings. + * cpuid.c: Added Atom Z3n00 (Bay Trail-T B2/B3) specific stepping 1. + * cpuid.c: Added Xeon D-1500 (Broadwell-DE) V2 stepping. + * cpuid.c: Corrected Atom Z8000 (Cherry Trail) with correct model, per + changes in its spec update. + * cpuid.c: Change the (0,6),(5,14) Skylake descriptions to be more vague + to reflect the larger set of existing processors now. + * cpuid.c: Add actual information for the (0,6),(4,14) Skylake + processors. + * cpuid.c: Add actual information for the (0,6),(5,14) Broadwell-E + processors. + * cpuid.c: Add actual information for the (0,6),(4,15) Broadwell and + Broadwell-EX processors. + * cpuid.c: Added vague mentions of Goldmont (0,6),(5,12) and (0,6),(5,15) + based on 325462 Table 35-1. + * cpuid.c: Add Atom S1200 (Centerton) under (0,6),(3,6) thanks to an + example provided by Jirka Hladky. + * cpuid.c: Added Eden to the list of possible meanings of VIA + (0,6),(6,13). An example provided by Daniel Wyatt shows that they + sometimes use the simple Eden brand for this architecture. + * cpuid.man: Added various new Intel documents used while making the + above changes. + * cpuid.c: Made -f - operate on stdin. + +Wed Jun 22 2016 Alan Cox <[email protected]> + * cpuid.c: Added out-of-memory checks to strregexp. + +Mon Oct 19 2015 Todd Allen <[email protected]> + * Updated cpuid.man's list of information sources with new sources used + in the 20151017 release (and one renamed source). + Sat Oct 17 2015 Todd Allen <[email protected]> * Made new release. * cpuid.c: Updated synth decoding for Broadwell processors. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20151017/FUTURE new/cpuid-20160814/FUTURE --- old/cpuid-20151017/FUTURE 2015-10-17 21:33:46.000000000 +0200 +++ new/cpuid-20160814/FUTURE 2016-08-13 22:32:44.000000000 +0200 @@ -1,6 +1,8 @@ -Intel: Atom S1200 (Centerton) and S12x9 (Briarwood) are based on Cedarview, but - the Intel docs provide no CPUID identification values. And I can find - no examples online. Does anyone know the CPUID family/model/steppings? +Intel: Skylake doesn't mention stepping numbers. I have one example system, + skylar. Add any unknowns to this file. +Intel: Atom S12x9 (Briarwood) is based on Cedarview, but the Intel docs provide + no CPUID identification values. And I can find no examples online. Does + anyone know the CPUID family/model/steppings? Intel: I can find no cpuid information on Atom C1000, Z2000, or E2000. (Possibly they are (0,6),(2,7) or (0,6),(3,5)?) AMD: Verify that (7,15, 0, 0, 1) really is steamroller. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20151017/Makefile new/cpuid-20160814/Makefile --- old/cpuid-20151017/Makefile 2015-10-17 22:04:31.000000000 +0200 +++ new/cpuid-20160814/Makefile 2016-08-14 19:46:59.000000000 +0200 @@ -7,7 +7,7 @@ CFL=$(CPPFLAGS) $(CFLAGS) $(CISA) -Wall -Wshadow -Wcast-align -Wredundant-decls -Wbad-function-cast -Wcast-qual -Wwrite-strings -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -D_FILE_OFFSET_BITS=64 -DVERSION=$(VERSION) PACKAGE=cpuid -VERSION=20151017 +VERSION=20160814 RELEASE=1 PROG=$(PACKAGE) @@ -26,16 +26,17 @@ SRCS=cpuid.c -OTHER_SRCS=Makefile $(PROG).man $(PACKAGE).proto.spec $(PACKAGE).spec \ +OTHER_SRCS=Makefile $(PROG).man cpuinfo2cpuid \ + $(PACKAGE).proto.spec $(PACKAGE).spec \ ChangeLog FUTURE LICENSE -OTHER_BINS=$(PROG).man +OTHER_BINS=$(PROG).man cpuinfo2cpuid.man REL_DIR=../$(shell date +%Y-%m-%d) WEB_DIR=/toad2/apps.mine/www/www/$(PROG) BUILDROOT= -default: $(PROG) $(PROG).man.gz +default: $(PROG) $(PROG).man.gz cpuinfo2cpuid cpuinfo2cpuid.man.gz $(PROG): cpuid.c Makefile $(CC) $(CFL) $(LDFLAGS) -o $@ cpuid.c @@ -43,16 +44,29 @@ $(PROG).man.gz: $(PROG).man gzip < $< > $@ -install: $(PROG) $(PROG).man.gz - install -D -s -m 755 $(PROG) $(BUILDROOT)/usr/bin/$(PROG) - install -D -m 444 $(PROG).man.gz $(BUILDROOT)/usr/share/man/man1/$(PROG).1.gz +cpuinfo2cpuid.man: cpuinfo2cpuid Makefile + pod2man -r "$(VERSION)" -c "" $< > $@ + +cpuinfo2cpuid.man.gz: cpuinfo2cpuid.man + gzip < $< > $@ + +install: $(PROG) $(PROG).man.gz cpuinfo2cpuid cpuinfo2cpuid.man.gz + install -D -s -m 755 $(PROG) $(BUILDROOT)/usr/bin/$(PROG) + install -D -m 444 $(PROG).man.gz $(BUILDROOT)/usr/share/man/man1/$(PROG).1.gz + install -D -m 755 cpuinfo2cpuid $(BUILDROOT)/usr/bin/cpuinfo2cpuid + install -D -m 444 cpuinfo2cpuid.man.gz $(BUILDROOT)/usr/share/man/man1/cpuinfo2cpuid.1.gz clean: rm -f $(PROG) $(PROG).i386 $(PROG).x86_64 - rm -f $(PACKAGE).spec $(PROG).man.gz + rm -f $(PROG).man.gz + rm -f cpuinfo2cpuid.man cpuinfo2cpuid.man.gz + rm -f $(PACKAGE).spec rm -f $(TARS) rm -f $(RPMS) rm -f $(DEBUG_RPMS) + rm -f $(PACKAGE)-*.src.tar.gz $(PACKAGE)-*.i386.tar.gz $(PACKAGE)-*.x86_64.tar.gz + rm -f $(PACKAGE)-*.src.rpm $(PACKAGE)-*.i386.rpm $(PACKAGE)-*.x86_64.rpm + rm -f $(PACKAGE)-debuginfo-*.i386.rpm $(PACKAGE)-debuginfo-*.x86_64.rpm # Todd's Development rules diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20151017/cpuid.c new/cpuid-20160814/cpuid.c --- old/cpuid-20151017/cpuid.c 2015-10-17 21:59:03.000000000 +0200 +++ new/cpuid-20160814/cpuid.c 2016-08-15 05:54:53.000000000 +0200 @@ -1,6 +1,7 @@ /* ** cpuid dumps CPUID information for each CPU. -** Copyright 2003,2004,2005,2006,2010,2011,2012,2013,2014,2015 by Todd Allen. +** Copyright 2003,2004,2005,2006,2010,2011,2012,2013,2014,2015,2016 by +** Todd Allen. ** ** This program is free software; you can redistribute it and/or ** modify it under the terms of the GNU General Public License @@ -88,6 +89,10 @@ if (status != 0) { size_t size = regerror(status, &re, NULL, 0); char* buffer = malloc(size + 1); + if (buffer == NULL || size + 1 == 0) { + fprintf(stderr, "%s: out of memory\n", program); + exit(1); + } regerror(status, &re, buffer, size); fprintf(stderr, "%s: cannot regcomp \"%s\"; error = %s\n", program, needle, buffer); @@ -97,6 +102,10 @@ if (status != 0 && status != REG_NOMATCH) { size_t size = regerror(status, &re, NULL, 0); char* buffer = malloc(size + 1); + if (buffer == NULL || size + 1 == 0) { + fprintf(stderr, "%s: out of memory\n", program); + exit(1); + } regerror(status, &re, buffer, size); fprintf(stderr, "%s: cannot regexec string \"%s\" with regexp \"%s\";" " error = %s\n", @@ -258,6 +267,7 @@ char brand[48]; char transmeta_info[48]; char override_brand[48]; + char soc_brand[48]; hypervisor_t hypervisor; struct mp { @@ -336,7 +346,8 @@ 0, 0, 0, 0, 0, 0, \ { 0, 0 }, \ { 0, 0 }, \ - 0, 0, 0, 0, 0, 0, "", "", "", \ + 0, 0, 0, 0, 0, 0, \ + "", "", "", "", \ HYPERVISOR_UNKNOWN, \ { NULL, -1, -1 }, \ { FALSE, \ @@ -2119,8 +2130,13 @@ FM ( 0, 6, 2,14, "Intel Xeon (Beckton), 45nm"); FMS ( 0, 6, 2,15, 2, "Intel Xeon E7-8800 / Xeon E7-4800 / Xeon E7-2800 (Westmere-EX A2), 32nm"); FM ( 0, 6, 2,15, "Intel Xeon E7-8800 / Xeon E7-4800 / Xeon E7-2800 (Westmere-EX), 32nm"); - FMS ( 0, 6, 3, 6, 1, "Intel Atom D2000/N2000 (Cedarview B1/B2/B3), 32nm"); - FM ( 0, 6, 3, 6, "Intel Atom D2000/N2000 (Cedarview), 32nm"); + FMS ( 0, 6, 3, 5, 1, "Intel Atom Z8000 (Cherry Trail C0), 14nm"); + FM ( 0, 6, 3, 5, "Intel Atom Z8000 (Cherry Trail), 14nm"); + // Intel docs (328198) do not provide any FMS for Centerton, but an example + // from [email protected] does. + FMS ( 0, 6, 3, 6, 1, "Intel Atom D2000/N2000 (Cedarview B1/B2/B3) / S1200 (Centerton B1), 32nm"); + FM ( 0, 6, 3, 6, "Intel Atom D2000/N2000 (Cedarview) / S1200 (Centerton B1), 32nm"); + FMS ( 0, 6, 3, 7, 1, "Intel Atom Z3000 (Bay Trail-T B2/B3), 22nm"); FMS ( 0, 6, 3, 7, 2, "Intel Pentium / Celeron (Bay Trail-M B1), 22nm"); FMS ( 0, 6, 3, 7, 3, "Intel Pentium N3500 / J2850 / Celeron N1700 / N1800 / N2800 / N2900 (Bay Trail-M B2/B3), 22nm"); FMSQ( 0, 6, 3, 7, 8, dC, "Intel Celeron N2800 / N2900 (Bay Trail-M C0), 22nm"); @@ -2175,7 +2191,7 @@ FMQ ( 0, 6, 4, 6, MC, "Intel Mobile Celeron 2900U (Mobile H) (Haswell), 22nm"); FMQ ( 0, 6, 4, 6, dP, "Intel Pentium G3000 (Desktop R) (Haswell), 22nm"); FM ( 0, 6, 4, 6, "Intel Core i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i5-4000 / Mobile Core i5-4000 / Mobile Core i7-4000 / Pentium G3000 / Celeron G1800 / Mobile Pentium 3500U/3600U/3500Y / Mobile Celeron 2900U / Xeon E3-1200 v3 (Desktop R/Mobile H) (Haswell), 22nm"); - // So far, all these (0,6), (4,7) processors are stepping G0, but the + // So far, all these (0,6),(4,7) processors are stepping G0, but the // Intel docs (332381, 332382) omit the stepping number for G0. FMQ ( 0, 6, 4, 7, dc, "Intel Core i7-5000 (Broadwell), 14nm"); FMQ ( 0, 6, 4, 7, Mc, "Intel Mobile Core i7-5000 (Broadwell), 14nm"); @@ -2183,23 +2199,39 @@ FM ( 0, 6, 4, 7, "Intel Core i7-5000 / Mobile Core i7-5000 / Xeon E3-1200 v4 (Broadwell), 14nm"); FM ( 0, 6, 4,10, "Intel Atom Z3400 (Merrifield), 22nm"); // no spec update; only 325462 Table 35-1 so far FMS ( 0, 6, 4,12, 0, "Intel Pentium N3000 / Celeron N3000 (Braswell C0), 14nm"); - FMS ( 0, 6, 4,12, 3, "Intel Atom Z8000 (Cherry Trail C0), 14nm"); - FM ( 0, 6, 4,12, "Intel Pentium N3000 / Celeron N3000 (Braswell) / Atom Z8000 (Cherry Trail), 14nm"); + FM ( 0, 6, 4,12, "Intel Pentium N3000 / Celeron N3000 (Braswell), 14nm"); + FMS ( 0, 6, 4,13, 0, "Intel Atom C2000 (Avoton A0/A1), 22nm"); FMS ( 0, 6, 4,13, 8, "Intel Atom C2000 (Avoton B0), 22nm"); FM ( 0, 6, 4,13, "Intel Atom C2000 (Avoton), 22nm"); - FM ( 0, 6, 4,14, "Intel Core / Xeon E3-1500m (Skylake), 14nm"); // no spec update; only 325462 Table 35-1 so far - FM ( 0, 6, 4,15, "Intel Xeon (Broadwell), 14nm"); // no spec update; only 325462 Table 35-1 so far - FM ( 0, 6, 5, 7, "Intel Xeon Phi Coprocessor (Knights Landing), 14nm"); // no spec update; only 325462 Table 35-1 so far + // Intel docs (332689) omit the stepping numbers for (0,6),(4,14) D1 & K1. + FMQ ( 0, 6, 4,14, dc, "Intel Core i3-6000U / i5-6000U / i7-6000U / m3-6Y00 / m5-6Y00 / m7-6Y00 (Skylake), 14nm"); + FMQ ( 0, 6, 4,14, dP, "Intel Pentium 4405U / Pentium 4405Y (Skylake), 14nm"); + FMQ ( 0, 6, 4,14, dC, "Intel Celeron 3800U / 39000U (Skylake), 14nm"); + FMQ ( 0, 6, 4,14, sX, "Intel Xeon E3-1500m (Skylake), 14nm"); // no spec update; only 325462 Table 35-1 so far + FM ( 0, 6, 4,14, "Intel Core i3-6000U / i5-6000U / i7-6000U / m3-6Y00 / m5-6Y00 / m7-6Y00 / Pentium 4405U / Pentium 4405Y / Celeron 3800U / 39000U / Xeon E3-1500m (Skylake), 14nm"); + // Intel docs (334208,333811) omit the stepping numbers for (0,6),(4,15) + // B0, M0 & R0. + FMQ ( 0, 6, 4,15, dc, "Intel Core i7-6800K / i7-6900K / i7-6900X (Broadwell-E), 14nm"); + FMQ ( 0, 6, 4,15, sX, "Intel Xeon E5-1600 / E5-2600 / E5-4600 v4 (Broadwell) / E7-4800 / E7-8800 v4 (Broadwell-EX), 14nm"); + FM ( 0, 6, 4,15, "Intel Core i7-6800K / i7-6900K / i7-6900X (Broadwell-E) / Xeon E5-1600 / E5-2500 / E5-4600 (Broadwell) / E7-4800 / E7-8800 v4 (Broadwell-EX), 14nm"); + // So far, all these (0,6),(5,7) processors are stepping B0, but the + // Intel docs (334646) omit the stepping number for B0. + FM ( 0, 6, 5, 7, "Intel Xeon Phi x200 (Knights Landing), 14nm"); FMS ( 0, 6, 5, 6, 1, "Intel Xeon D-1500 (Broadwell-DE U0), 14nm"); FMS ( 0, 6, 5, 6, 2, "Intel Xeon D-1500 (Broadwell-DE V1), 14nm"); + FMS ( 0, 6, 5, 6, 3, "Intel Xeon D-1500 (Broadwell-DE V2), 14nm"); FM ( 0, 6, 5, 6, "Intel Xeon D-1500 (Broadwell-DE), 14nm"); FM ( 0, 6, 5,10, "Intel Atom Z3400 (Moorefield), 22nm"); // no spec update; only 325462 Table 35-1 so far + FM ( 0, 6, 5,12, "Intel Atom (Goldmont), 14nm"); // no spec update; only 325462 Table 35-1 so far FM ( 0, 6, 5,13, "Intel Atom X3-C3000 (SoFIA), 22nm"); // no spec update; only 325462 Table 35-1 so far - // So far, all these (0,6), (5,14) processors are stepping R0, but the - // Intel docs (332689) omit the stepping number for R0. - FMQ ( 0, 6, 5,14, dc, "Intel Core i5-6600K / i7-6700K (Skylake), 14nm"); - FMQ ( 0, 6, 5,14, sX, "Intel Xeon E3-1500m (Skylake), 14nm"); // no spec update; only 325462 Table 35-1 so far - FM ( 0, 6, 5,14, "Intel Core i5-6600K / i7-6700K / Xeon E3-1500m (Skylake), 14nm"); + FM ( 0, 6, 5,15, "Intel Atom (Goldmont), 14nm"); // no spec update; only 325462 Table 35-1 so far + // Intel docs (332689,333133) omit the stepping numbers for (0,6),(5,14) + // R0 & S0. + FMQ ( 0, 6, 5,14, dc, "Intel Core i3-6000 / i5-6000 / i7-6000 (Skylake), 14nm"); + FMQ ( 0, 6, 5,14, dP, "Intel Pentium G4000 (Skylake), 14nm"); + FMQ ( 0, 6, 5,14, dC, "Intel Celeron G3900 (Skylake), 14nm"); + FMQ ( 0, 6, 5,14, sX, "Intel Xeon E3-1200 v5 (Skylake), 14nm"); + FM ( 0, 6, 5,14, "Intel Core i3-6000 / i5-6000 / i7-6000 / Pentium G4000 / Celeron G3900 / Xeon E3-1200 (Skylake), 14nm"); FQ ( 0, 6, sX, "Intel Xeon (unknown model)"); FQ ( 0, 6, se, "Intel Xeon (unknown model)"); FQ ( 0, 6, MC, "Intel Mobile Celeron (unknown model)"); @@ -2978,9 +3010,9 @@ FMS(0, 6, 0, 9, 7, "VIA C3 / Eden ESP 7000/8000/10000 (Nehemiah WinChip C5XL core)"); FM (0, 6, 0, 9, "VIA C3 / C3-M / Eden-N (Antaur WinChip C5P core)"); FM (0, 6, 0,10, "VIA C7 / C7-M (Esther WinChip C5J core)"); - FM (0, 6, 0,13, "VIA C7 / C7-M / C7-D (Esther unknown core)"); + FM (0, 6, 0,13, "VIA C7 / C7-M / C7-D / Eden (Esther unknown core)"); FM (0, 6, 0,15, "VIA Nano (Isaiah)"); - F (0, 6, "VIA C3 / C3-M / C7 / C7-M / Eden ESP 7000/8000/10000 / Nano (unknown model)"); + F (0, 6, "VIA C3 / C3-M / C7 / C7-M / Eden / Eden ESP 7000/8000/10000 / Nano (unknown model)"); DEFAULT ("unknown"); printf("\n"); } @@ -3745,7 +3777,7 @@ { if (vendor == VENDOR_CYRIX || vendor == VENDOR_VIA) { switch (value) { - case 0x70: printf("TLB: 4k pages, 4-way, 32 entries"); return; + case 0x70: printf("TLB: 4K pages, 4-way, 32 entries"); return; case 0x74: printf("Cyrix-specific: ?"); return; case 0x77: printf("Cyrix-specific: ?"); return; case 0x80: printf("L1 cache: 16K, 4-way, 16 byte lines"); return; @@ -3821,6 +3853,7 @@ case 0x60: printf("L1 data cache: 16K, 8-way, 64 byte lines"); break; case 0x61: printf("instruction TLB: 4K pages, 48 entries"); break; case 0x63: printf("data TLB: 1G pages, 4-way, 4 entries"); break; + case 0x64: printf("data TLB: 4K pages, 4-way, 512 entries"); break; case 0x66: printf("L1 data cache: 8K, 4-way, 64 byte lines"); break; case 0x67: printf("L1 data cache: 16K, 4-way, 64 byte lines"); break; case 0x68: printf("L1 data cache: 32K, 4-way, 64 byte lines"); break; @@ -3871,6 +3904,7 @@ case 0xc1: printf("L2 TLB: 4K/2M pages, 8-way, 1024 entries"); break; case 0xc2: printf("data TLB: 2M/4M pages, 4-way, 16 entries"); break; case 0xc3: printf("L2 TLB: 4K/2M pages, 6-way, 1536 entries"); break; + case 0xc4: printf("data TLB: 2M/4M pages, 4-way, 32 entries"); break; case 0xca: printf("L2 TLB: 4K pages, 4-way, 512 entries"); break; case 0xd0: printf("L3 cache: 512K, 4-way, 64 byte lines"); break; case 0xd1: printf("L3 cache: 1M, 4-way, 64 byte lines"); break; @@ -4072,9 +4106,11 @@ static named_item names[] = { { "FSGSBASE instructions" , 0, 0, bools }, { "IA32_TSC_ADJUST MSR supported" , 1, 1, bools }, + { "SGX: Software Guard Extensions supported", 2, 2, bools }, { "BMI instruction" , 3, 3, bools }, { "HLE hardware lock elision" , 4, 4, bools }, { "AVX2: advanced vector extensions 2" , 5, 5, bools }, + { "FDP_EXCPTN_ONLY" , 6, 6, bools }, { "SMEP supervisor mode exec protection" , 7, 7, bools }, { "BMI2 instructions" , 8, 8, bools }, { "enhanced REP MOVSB/STOSB" , 9, 9, bools }, @@ -4105,8 +4141,12 @@ { static named_item names[] = { { "PREFETCHWT1" , 0, 0, bools }, + { "UMIP: user-mode instruction prevention" , 2, 2, bools }, { "PKU protection keys for user-mode" , 3, 3, bools }, { "OSPKE CR4.PKE and RDPKRU/WRPKRU" , 4, 4, bools }, + { "BNDLDX/BNDSTX MAWAU value in 64-bit mode", 17, 21, NIL_IMAGES }, + { "RDPID: read processor D supported" , 22, 22, bools }, + { "SGX_LC: SGX launch config supported" , 30, 30, bools }, }; print_names(value, names, LENGTH(names, named_item), @@ -4199,20 +4239,26 @@ static void print_d_0_eax(unsigned int value) { - static ccstring all_or_none[] = { "false", - "unexpected: 001b", - "unexpected: 010b", - "unexpected: 011b", - "unexpected: 100b", - "unexpected: 101b", - "unexpected: 110b", - "true" }; - static named_item names[] - = { { " XCR0 field supported: x87 state" , 0, 0, bools }, - { " XCR0 field supported: SSE state" , 1, 1, bools }, - { " XCR0 field supported: AVX state" , 2, 2, bools }, - { " XCR0 field supported: AVX-512 state" , 5, 7, all_or_none }, - { " XCR0 field supported: PKRU state" , 9, 9, bools }, + /* + ** State component bitmaps in general are described in 325462: Intel 64 and + ** IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A, + ** 2B, 2C, 3A, 3B, and 3C, section 13.1: XSAVE-Supported Features and + ** State-Component Bitmaps. This leaf describes which of the bits are + ** actually supported by the hardware, and is described better in 1.32: + ** Enumeration of CPU Support for XSAVE Instructions and XSAVE-Supported + ** Features. + */ + static named_item names[] + = { { " XCR0 supported: x87 state" , 0, 0, bools }, + { " XCR0 supported: SSE state" , 1, 1, bools }, + { " XCR0 supported: AVX state" , 2, 2, bools }, + { " XCR0 supported: MPX BNDREGS" , 3, 3, bools }, + { " XCR0 supported: MPX BNDCSR" , 4, 4, bools }, + { " XCR0 supported: AVX-512 opmask" , 5, 5, bools }, + { " XCR0 supported: AVX-512 ZMM_Hi256" , 6, 6, bools }, + { " XCR0 supported: AVX-512 Hi16_ZMM" , 7, 7, bools }, + { " IA32_XSS supported: PT state" , 8, 8, bools }, + { " XCR0 supported: PKRU state" , 9, 9, bools }, }; print_names(value, names, LENGTH(names, named_item), @@ -4236,8 +4282,8 @@ static void print_d_n_ecx(unsigned int value) { - static ccstring which[] = { "XCR0", - "IA32_XSS" }; + static ccstring which[] = { "XCR0 (user state)", + "IA32_XSS (supervisor state)" }; static named_item names[] = { { "supported in IA32_XSS or XCR0" , 0, 0, which }, @@ -4255,19 +4301,19 @@ /* ** The XSAVE areas are explained in 325462: Intel 64 and IA-32 Architectures ** Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, and - ** 3C, section 13.1: XSAVE-Supported Features and State-Component Bitmaps - ** and again in 13.3: Enabling the XSAVE Feature Set and XSAVE-Enabled - ** Features. + ** 3C, section 13.1: XSAVE-Supported Features and State-Component Bitmaps. + ** These align with the supported feature names[] in print_d_0_eax() for + ** values > 1. */ static ccstring features[64] = { /* 0 => */ "internal error", /* 1 => */ "internal error", /* 2 => */ "AVX/YMM", - /* 3 => */ "unknown", - /* 4 => */ "unknown", + /* 3 => */ "MPX BNDREGS", + /* 4 => */ "MPX BNDCSR", /* 5 => */ "AVX-512 opmask", /* 6 => */ "AVX-512 ZMM_Hi256", - /* 7 => */ "AVX-512 Hi16-ZMM", - /* 8 => */ "unknown", + /* 7 => */ "AVX-512 Hi16_ZMM", + /* 8 => */ "PT", /* 9 => */ "PKRU", /* 10 => */ "unknown", /* 11 => */ "unknown", @@ -4353,7 +4399,19 @@ } static void -print_10_1_eax(unsigned int value) +print_10_0_ebx(unsigned int value) +{ + static named_item names[] + = { { "L3 cache allocation technology supported", 1, 1, bools }, + { "L2 cache allocation technology supported", 2, 2, bools }, + }; + + print_names(value, names, LENGTH(names, named_item), + /* max_len => */ 0); +} + +static void +print_10_n_eax(unsigned int value) { static named_item names[] = { { "length of capacity bit mask" , 0, 4, NIL_IMAGES }, @@ -4364,7 +4422,7 @@ } static void -print_10_1_ecx(unsigned int value) +print_10_n_ecx(unsigned int value) { static named_item names[] = { { "infrequent updates of COS" , 1, 1, bools }, @@ -4376,7 +4434,7 @@ } static void -print_10_1_edx(unsigned int value) +print_10_n_edx(unsigned int value) { static named_item names[] = { { "highest COS number supported" , 0, 15, NIL_IMAGES }, @@ -4387,6 +4445,60 @@ } static void +print_12_0_eax(unsigned int value) +{ + static named_item names[] + = { { "SGX1 supported" , 0, 0, bools }, + { "SGX2 supported" , 1, 1, bools }, + }; + + print_names(value, names, LENGTH(names, named_item), + /* max_len => */ 38); +} + +static void +print_12_0_ebx(unsigned int value) +{ + /* + ** MISCSELECT is described in Table 38-4: Bit Vector Layout of MISCSELECT + ** Field of Extended Information. + */ + static named_item names[] + = { { "MISCSELECT.EXINFO supported: #PF & #GP" , 0, 0, bools }, + }; + + print_names(value, names, LENGTH(names, named_item), + /* max_len => */ 38); +} + +static void +print_12_0_edx(unsigned int value) +{ + static named_item names[] + = { { "MaxEnclaveSize_Not64 (log2)" , 0, 7, NIL_IMAGES }, + { "MaxEnclaveSize_64 (log2)" , 8, 15, NIL_IMAGES }, + }; + + print_names(value, names, LENGTH(names, named_item), + /* max_len => */ 38); +} + +static void +print_12_n_1_ecx(unsigned int value) +{ + static ccstring props[16] = { /* 0 => */ "enumerated as 0", + /* 1 => */ "confidentiality & integrity" + " protection" }; + + static named_item names[] + = { { "section property" , 0, 3, props }, + }; + + print_names(value, names, LENGTH(names, named_item), + /* max_len => */ 23); +} + +static void print_14_0_ebx(unsigned int value) { static named_item names[] @@ -4394,6 +4506,8 @@ { "configurable PSB & cycle-accurate" , 1, 1, bools }, { "IP & TraceStop filtering; PT preserve" , 2, 2, bools }, { "MTC timing packet; suppress COFI-based" , 3, 3, bools }, + { "PTWRITE support" , 4, 4, bools }, + { "power event trace support" , 5, 5, bools }, }; print_names(value, names, LENGTH(names, named_item), @@ -4473,6 +4587,21 @@ } static void +print_17_0_ebx(unsigned int value) +{ + static ccstring schemes[] = { /* 0 => */ "industry standard", + /* 1 => */ "assigned by intel" }; + + static named_item names[] + = { { "vendor id" , 0, 15, NIL_IMAGES }, + { "vendor scheme" , 16, 16, schemes }, + }; + + print_names(value, names, LENGTH(names, named_item), + /* max_len => */ 0); +} + +static void print_40000002_ecx_xen(unsigned int value) { static named_item names[] @@ -5097,7 +5226,7 @@ = { { "line size (bytes)" , 0, 7, NIL_IMAGES }, { "lines per tag" , 8, 15, NIL_IMAGES }, { "associativity" , 16, 23, NIL_IMAGES }, - { "size (Kb)" , 24, 31, NIL_IMAGES }, + { "size (KB)" , 24, 31, NIL_IMAGES }, }; printf(" L1 data cache information (0x80000005/ecx):\n"); @@ -5112,7 +5241,7 @@ = { { "line size (bytes)" , 0, 7, NIL_IMAGES }, { "lines per tag" , 8, 15, NIL_IMAGES }, { "associativity" , 16, 23, NIL_IMAGES }, - { "size (Kb)" , 24, 31, NIL_IMAGES }, + { "size (KB)" , 24, 31, NIL_IMAGES }, }; printf(" L1 instruction cache information (0x80000005/edx):\n"); @@ -5176,7 +5305,7 @@ = { { "line size (bytes)" , 0, 7, NIL_IMAGES }, { "lines per tag" , 8, 11, NIL_IMAGES }, { "associativity" , 12, 15, l2_assoc }, - { "size (Kb)" , 16, 31, NIL_IMAGES }, + { "size (KB)" , 16, 31, NIL_IMAGES }, }; printf(" L2 unified cache information (0x80000006/ecx):\n"); @@ -5197,7 +5326,7 @@ = { { "line size (bytes)" , 0, 7, NIL_IMAGES }, { "lines per tag" , 8, 11, NIL_IMAGES }, { "associativity" , 12, 15, l2_assoc }, - { "size (in 512Kb units)" , 18, 31, NIL_IMAGES }, + { "size (in 512KB units)" , 18, 31, NIL_IMAGES }, }; printf(" L3 cache information (0x80000006/edx):\n"); @@ -5682,7 +5811,8 @@ printf(" -f FILE, --file=FILE read raw hex information (-r output) from" " FILE instead\n"); printf(" of from executions of the cpuid" - " instruction\n"); + " instruction.\n"); + printf(" If FILE is '-', read from stdin.\n"); printf(" -h, -H, --help display this help information\n"); printf(" -i, --inst use the CPUID instruction: The information" " it provides\n"); @@ -5935,13 +6065,14 @@ printf(" XSAVE features (0xd/0):\n"); printf(" XCR0 lower 32 bits valid bit field mask = 0x%08x\n", words[WORD_EAX]); + printf(" XCR0 upper 32 bits valid bit field mask = 0x%08x\n", + words[WORD_EDX]); print_d_0_eax(words[WORD_EAX]); + // No bits current are defined in d_0_edx printf(" bytes required by fields in XCR0 = 0x%08x (%u)\n", words[WORD_EBX], words[WORD_EBX]); printf(" bytes required by XSAVE/XRSTOR area = 0x%08x (%u)\n", words[WORD_ECX], words[WORD_ECX]); - printf(" XCR0 upper 32 bits valid bit field mask = 0x%08x\n", - words[WORD_EDX]); } else if (try == 1) { printf(" XSAVE features (0xd/1):\n"); print_d_1_eax(words[WORD_EAX]); @@ -5977,18 +6108,48 @@ } } else if (reg == 0x10) { if (try == 0) { - printf(" Quality of Service Enforcement Resource Type (0x10/0):\n"); - printf(" Maximum range of RMID = %u\n", words[WORD_EBX]); - } else if (try == 1) { - printf(" L3 Cache Quality of Service Enforcement (0x10/1):\n"); - print_10_1_eax(words[WORD_EAX]); + printf(" Resource Director Technology allocation (0x10/0):\n"); + print_10_0_ebx(words[WORD_EBX]); + } else if (try == 1 || try == 2) { + if (try == 1) { + printf(" L3 Cache Allocation Technology (0x10/1):\n"); + } else if (try == 2) { + printf(" L2 Cache Allocation Technology (0x10/2):\n"); + } + print_10_n_eax(words[WORD_EAX]); printf(" Bit-granular map of isolation/contention = 0x%08x\n", words[WORD_EBX]); - print_10_1_ecx(words[WORD_EAX]); - print_10_1_edx(words[WORD_EAX]); + print_10_n_ecx(words[WORD_EAX]); + print_10_n_edx(words[WORD_EAX]); } else { print_reg_raw(reg, try, words); } + } else if (reg == 0x12) { + if (try == 0) { + printf(" SGX capability (0x12/0):\n"); + print_12_0_eax(words[WORD_EAX]); + print_12_0_ebx(words[WORD_EBX]); + print_12_0_edx(words[WORD_EDX]); + } else if (try == 1) { + printf(" SGX attributes (0x12/1):\n"); + printf(" ECREATE SECS.ATTRIBUTES valid bit mask =" + " 0x%08x%08x%08x%08x\n", + words[WORD_EDX], + words[WORD_ECX], + words[WORD_EBX], + words[WORD_EAX]); + } else { + if ((words[WORD_EAX] & 0xf) == 1) { + printf(" SGX EPC enumeration (0x12/n):\n"); + printf(" section physical address = 0x%08x%08x\n", + words[WORD_EBX], words[WORD_EAX] & 0xfffff000); + printf(" section size = 0x%08x%08x\n", + words[WORD_EDX], words[WORD_ECX] & 0xfffff000); + print_12_n_1_ecx(words[WORD_ECX]); + } else { + print_reg_raw(reg, try, words); + } + } } else if (reg == 0x14) { if (try == 0) { printf(" Intel Processor Trace (0x14):\n"); @@ -6009,6 +6170,24 @@ print_16_eax(words[WORD_EAX]); print_16_ebx(words[WORD_EBX]); print_16_ecx(words[WORD_ECX]); + } else if (reg == 0x17) { + if (try == 0) { + printf(" system-on-chip vendor attribute (0x17/0):\n"); + print_17_0_ebx(words[WORD_EBX]); + printf(" project id = 0x%08x (%u)\n", + words[WORD_ECX], words[WORD_ECX]); + printf(" stepping id = 0x%08x (%u)\n", + words[WORD_EDX], words[WORD_EDX]); + } else if (try == 1) { + memcpy(&stash->soc_brand[0], words, sizeof(unsigned int)*WORD_NUM); + } else if (try == 2) { + memcpy(&stash->soc_brand[16], words, sizeof(unsigned int)*WORD_NUM); + } else if (try == 3) { + memcpy(&stash->soc_brand[32], words, sizeof(unsigned int)*WORD_NUM); + printf(" SoC brand = \"%s\"\n", stash->soc_brand); + } else { + print_reg_raw(reg, try, words); + } } else if (reg == 0x40000000) { // max already set to words[WORD_EAX] printf(" hypervisor_id = \"%-4.4s%-4.4s%-4.4s\"\n", @@ -6230,7 +6409,7 @@ #ifdef USE_KERNEL_SCHED_SETAFFINITY /* ** The interface for sched_setaffinity and cpusets has changed many - ** times. Insulate this tool from it all that by calling the system + ** times. Insulate this tool from all that by calling the system ** service directly. */ unsigned int mask[MAX_CPUS / (sizeof(unsigned int)*8)]; @@ -6567,9 +6746,23 @@ unsigned int mask = words[WORD_EBX]; print_header(reg, 0, raw); print_reg(reg, words, raw, 0, &stash); - if (BIT_EXTRACT_LE(mask, 1, 2)) { - real_get(cpuid_fd, reg, words, 1, FALSE); - print_reg(reg, words, raw, 1, &stash); + unsigned int try; + for (try = 1; try < 32; try++) { + if (mask & (1 << try)) { + real_get(cpuid_fd, reg, words, try, FALSE); + print_reg(reg, words, raw, try, &stash); + } + } + } else if (reg == 0x12) { + unsigned int mask = words[WORD_EAX]; + print_header(reg, 0, raw); + print_reg(reg, words, raw, 0, &stash); + unsigned int try; + for (try = 1; try < 33; try++) { + if (mask & (1 << (try-1))) { + real_get(cpuid_fd, reg, words, try, FALSE); + print_reg(reg, words, raw, try, &stash); + } } } else if (reg == 0x14) { unsigned int try = 0; @@ -6584,6 +6777,19 @@ if (try > max_tries) break; real_get(cpuid_fd, reg, words, try, FALSE); } + } else if (reg == 0x17) { + unsigned int try = 0; + unsigned int max_tries; + for (;;) { + print_header(reg, try, raw); + print_reg(reg, words, raw, try, &stash); + if (try == 0) { + max_tries = words[WORD_EAX]; + } + try++; + if (try > max_tries) break; + real_get(cpuid_fd, reg, words, try, FALSE); + } } else if (reg == 0x40000003 && stash.hypervisor == HYPERVISOR_XEN) { unsigned int try = 0; for (; try <= 2; try++) { @@ -6713,12 +6919,17 @@ unsigned int try8000001d = -1; code_stash_t stash = NIL_STASH; - FILE* file = fopen(filename, "r"); - if (file == NULL) { - fprintf(stderr, - "%s: unable to open %s; errno = %d (%s)\n", - program, filename, errno, strerror(errno)); - exit(1); + FILE* file; + if (strcmp(filename, "-") == 0) { + file = stdin; + } else { + file = fopen(filename, "r"); + if (file == NULL) { + fprintf(stderr, + "%s: unable to open %s; errno = %d (%s)\n", + program, filename, errno, strerror(errno)); + exit(1); + } } while (!feof(file)) { @@ -6816,7 +7027,9 @@ do_final(raw, debug, &stash); } - fclose(file); + if (file != stdin) { + fclose(file); + } } int diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20151017/cpuid.man new/cpuid-20160814/cpuid.man --- old/cpuid-20151017/cpuid.man 2015-10-17 22:05:03.000000000 +0200 +++ new/cpuid-20160814/cpuid.man 2016-08-15 05:56:06.000000000 +0200 @@ -1,7 +1,7 @@ .\" -.\" $Id: cpuid.man,v 20151017 2015/10/17 14:04:27 todd $ +.\" $Id: cpuid.man,v 20151017 2016/08/14 21:55:40 todd $ .\" -.TH CPUID 1 "17 Oct 2015" "20151017" +.TH CPUID 1 "14 Aug 2016" "20160814" .SH NAME cpuid \- Dump CPUID information for each CPU .SH SYNOPSIS @@ -79,7 +79,7 @@ .TP 8 .I -f \fIFILE\fR, --file=\fIFILE\fR Read raw hex information from FILE instead of from executions of the cpuid -instruction. +instruction. If the filename is '-', instead read from standard input. .TP 8 .I -h, -H, --help Display help information. @@ -366,6 +366,9 @@ .br 326774: Intel Xeon Processor E3-1200 v2 Product Family Specification Update .br +328198: Intel Atom Processor S1200 Product Family for Microserver +Specification Update +.br 328205: Intel Xeon Phi Coprocessor x100 Product Family Specification Update .br 328899: Desktop 4th Generation Intel Core Processor Family Specification Update @@ -376,9 +379,14 @@ .br 329460: Intel Atom Processor C2000 Product Family Specification Update .br +329597: Intel Xeon Processor E7 v2 Product Family Specification Update +.br 330785: Intel Xeon Processor E5 v3 Product Family Specification Update .br -330836: Intel Core M Processor Family Specification Update +330836: 5th Generation Intel Core Processor Family, +Intel Core M Processor Family, +Mobile Intel Pentium Processor Family, and +Mobile Intel Celeron Processor Family Specification Update .br 330841: Intel Core i7 Processor Family for LGA2011-v3 Socket Specification Update .br @@ -393,6 +401,19 @@ .br 332381: Mobile/Desktop 5th Generation Intel Core Processor Family Specification Update +.br +332689: 6th Generation Intel Core Processor Family Specification Update +.br +333133: Intel Xeon Processor E3-1200 v5 Product Family Specification Update +.br +333811: Intel Xeon Processor E5-2600 v4 Product Family Specification Update +.br +334165: Intel Xeon Processor E7-8800/4800 v4 Product Family Specification Update +.br +334208: Intel Core i7 Processor Family for LGA2011-v3 Socket Specification Update +.br +334646: Intel Xeon Phi Processor x200 Product Family +Preliminary Specification Update .RE Information on the CPUID instruction and on specific CPUs is available from diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20151017/cpuid.proto.spec new/cpuid-20160814/cpuid.proto.spec --- old/cpuid-20151017/cpuid.proto.spec 2010-09-02 00:41:29.000000000 +0200 +++ new/cpuid-20160814/cpuid.proto.spec 2016-08-14 19:36:05.000000000 +0200 @@ -28,4 +28,6 @@ %defattr(-,root,root) %{_bindir}/cpuid %{_mandir}/man1/cpuid.1.gz +%{_bindir}/cpuinfo2cpuid +%{_mandir}/man1/cpuinfo2cpuid.1.gz %doc ChangeLog FUTURE LICENSE diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20151017/cpuid.spec new/cpuid-20160814/cpuid.spec --- old/cpuid-20151017/cpuid.spec 2015-10-17 22:07:17.000000000 +0200 +++ new/cpuid-20160814/cpuid.spec 2016-08-15 05:58:13.000000000 +0200 @@ -1,4 +1,4 @@ -%define version 20151017 +%define version 20160814 %define release 1 Summary: dumps CPUID information about the CPU(s) Name: cpuid @@ -30,4 +30,6 @@ %defattr(-,root,root) %{_bindir}/cpuid %{_mandir}/man1/cpuid.1.gz +%{_bindir}/cpuinfo2cpuid +%{_mandir}/man1/cpuinfo2cpuid.1.gz %doc ChangeLog FUTURE LICENSE diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20151017/cpuinfo2cpuid new/cpuid-20160814/cpuinfo2cpuid --- old/cpuid-20151017/cpuinfo2cpuid 1970-01-01 01:00:00.000000000 +0100 +++ new/cpuid-20160814/cpuinfo2cpuid 2016-08-14 19:37:51.000000000 +0200 @@ -0,0 +1,149 @@ +#!/usr/bin/perl + +use autodie; +use strict; +use utf8; +use warnings qw(all); + +use Getopt::Long; +use Pod::Usage; + +my $vendor = ''; +my $family = ''; +my $model = ''; +my $stepping = ''; +my $help; + +GetOptions( + q(help) => \$help, + q(vendor=s) => \$vendor, + q(family=i) => \$family, + q(model=i) => \$model, + q(stepping=i) => \$stepping, +) or pod2usage(q(-verbose) => 1); +pod2usage(q(-verbose) => 1) if $help; + +if ( $vendor ne '' or $family ne '' or $model ne '' or $stepping ne '' ) { + if ( $vendor ne 'GenuineIntel' and $vendor ne 'AuthenticAMD' ) { + print STDERR "vendor has to be either \"GenuineIntel\" or \"AuthenticAMD\"\n"; + pod2usage(q(-verbose) => 1); + } + if ( $vendor eq '' or $family eq '' or $model eq '' or $stepping eq '' ) { + print STDERR "When specifying input manually all input values \"vendor, family, model and stepping\" has to be specified\n"; + pod2usage(q(-verbose) => 1); + } +} else { + # Read cpuinfo from STDIN + while (<STDIN>) { + if (/^vendor_id\s*: (.*)$/) { + $vendor = $1 + } + if (/^cpu family\s*: (.*)$/) { + $family = $1 + } + if (/^model\s*: (.*)$/) { + $model = $1 + } + if (/^stepping\s*: (.*)$/) { + $stepping = $1 + } + } +} + +my $xfamily = int($family / 16); +$family = $family % 16; + +my $xmodel = int($model / 16); +$model = $model % 16; + +my $eax = ( (($xfamily & 0xff) << 20) + + (($xmodel & 0xf) << 16) + + (($family & 0xf) << 8) + + (($model & 0xf) << 4) + + (($stepping & 0xf) << 0)); + +printf("CPU:\n"); +if ($vendor eq "GenuineIntel") { + printf(" 0x%08x 0x%02x: eax=0x%08x ebx=0x%08x ecx=0x%08x edx=0x%08x\n", + 0, 0, 1, 0x756e6547, 0x6c65746e, 0x49656e69); +} elsif ($vendor eq "AuthenticAMD") { + printf(" 0x%08x 0x%02x: eax=0x%08x ebx=0x%08x ecx=0x%08x edx=0x%08x\n", + 0, 0, 1, 0x68747541, 0x444d4163, 0x69746e65); +} +printf(" 0x%08x 0x%02x: eax=0x%08x ebx=0x%08x ecx=0x%08x edx=0x%08x\n", + 1, 0, $eax, 0, 0, 0); + +__END__ + +=pod + +=head1 NAME + +cpuinfo2cpuid + +=head1 SYNOPSIS + +cpuinfo2cpuid + + or + +cpuinfo2cpuid -help + + or + +cpuinfo2cpuid -vendor=<GenuineIntel|AuthenticAMD> -family=<num> -model=<num> -stepping=<num> + +=head1 DESCRIPTION + +Expects /proc/cpuinfo data on stdin and converts it to cpuid-like HEX data structure suitable as the input for cpuid -f <file> utility. +Alternatively, user can specify CPU vendor, family, model and stepping on the command line. + +=head1 OPTIONS + +=over 4 + +=item -help + +Displays a brief help message. + +=item -vendor + +CPU vendor. Can be either GenuineIntel or AuthenticAMD. + +=item -family + +CPU family in decimal notation. + +=item -model + +CPU model in decimal notation. + +=item -stepping + +CPU stepping in decimal notation. + + +=item -help + +Displays a brief help message. + + +=back + +=head1 LIMITATIONS + +Only Intel & AMD cpuinfo data are supported at the moment. + +=head1 EXAMPLES + +cpuinfo2cpuid < /proc/cpuinfo | cpuid -f - + +Specifying CPU vendor, family, model and stepping on command line + +cpuinfo2cpuid.pl -vendor=GenuineIntel -family=6 -model=58 -stepping=9 | cpuid -f - + +=head1 AUTHOR + +Todd Allen <[email protected]>, Jirka Hladky <[email protected]> + +=cut
