Hi :)

El Martes, 30 de Mayo de 2006 20:09, Alexei_Roudnev escribió:
> It is transparent for the user's processes, so why do you expect any
> changes in gcc?


Well, if Woodcrest is a new type of processor (even though it's based on 
Xeon), it might have new registers, ... that have to be implemented in gcc. 
If it's not implemented in gcc, you might not get all the performance you 
might be looking for/expecting.

Just as you can, for example, specify:

        gcc  -mtune=pentium4

        gcc  -mtune=prescott

        gcc  -mtune=nocona



http://gcc.gnu.org/onlinedocs/gcc-4.1.1/gcc/i386-and-x86_002d64-Options.html#i386-and-x86_002d64-Options

pentium4, pentium4m
        Intel Pentium4 CPU with MMX, SSE and SSE2 instruction set support. 
prescott
        Improved version of Intel Pentium4 CPU with MMX, SSE, SSE2 and SSE3
        instruction set support. 
nocona
        Improved version of Intel Pentium4 CPU with 64-bit extensions, MMX, SSE,
        SSE2 and SSE3 instruction set support.



Maybe there's a:

        gcc  -mtune=woodcrest


The question would be: is there a  -mtune=woodcrest?

TIA

   Rafa


> ----- Original Message -----

> Hi :)
>
> El Lunes, 29 de Mayo de 2006 11:59, Eberhard Moenkeberg escribió:
> > Hi,
> >
> > On Mon, 29 May 2006, Rafa [iso-8859-15] Grimn wrote:
> > > Does anybody know whether Intel's Woodcrest processors will be
>
> supported?
>
> > > It's a dual core Xeon processor.
> > >
> > > Would it be a x86-64?
> > >
> > > Any glitches, gotchas, advice regarding: kernel, glibc, gcc, ...?
> >
> > I have some new Dell PE1850 with dual core Xeon CPUs (2 sockets, showing
> > 8 CPUs with HT enabled):
> >
> > zim01:0 11:56:09 ~ # cat /etc/SuSE-release
> > SUSE LINUX 10.0 (X86-64)
> > VERSION = 10.0
> > zim01:0 11:56:26 ~ # uname -a
> > Linux zim01 2.6.13-15.8-smp #1 SMP Tue Feb 7 11:07:24 UTC 2006 x86_64
> > x86_64 x86_64 GNU/Linux
> > zim01:0 11:56:50 ~ #
> >
> > /proc/cpuinfo says:
>
> [...]
>
> Thanks, but do you know if there would be any modifications to glibc, gcc,
> kernel, ... ? I guess some registers have changed/been added to the CPU
> (chip) but haven't found any info regarding support by gcc.
>
> TIA
>
>   Rafa

-- 
50% of all statistics are inaccurate.

OpenWengo: rgriman

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