Author: kaloz Date: 2015-03-19 11:25:44 +0100 (Thu, 19 Mar 2015) New Revision: 44882
Added: trunk/target/linux/mvebu/config-4.0 trunk/target/linux/mvebu/patches-4.0/ Removed: trunk/target/linux/mvebu/patches-4.0/019-mtd-nand-pxa3xx-Fix-PIO-FIFO-draining.patch trunk/target/linux/mvebu/patches-4.0/020-ARM-mvebu-Add-a-number-of-pinctrl-functions.patch trunk/target/linux/mvebu/patches-4.0/021-ARM-mvebu-Add-Armada-385-Access-Point-Development-Bo.patch trunk/target/linux/mvebu/patches-4.0/023-pinctrl-mvebu-a38x-Add-UART1-muxing-options.patch trunk/target/linux/mvebu/patches-4.0/024-ARM-mvebu-a38x-Fix-node-names.patch trunk/target/linux/mvebu/patches-4.0/200-gpio_mvebu_checkpatch_fixes.patch trunk/target/linux/mvebu/patches-4.0/201-gpio_mvebu_fix_probe_cleanup_on_error.patch Modified: trunk/target/linux/mvebu/patches-4.0/001-build_mamba_dts.patch trunk/target/linux/mvebu/patches-4.0/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch trunk/target/linux/mvebu/patches-4.0/051-leds_tlc59116_add_driver.patch trunk/target/linux/mvebu/patches-4.0/102-revert_i2c_delay.patch trunk/target/linux/mvebu/patches-4.0/202-gpio_mvebu_add_limited_pwm_support.patch trunk/target/linux/mvebu/patches-4.0/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch trunk/target/linux/mvebu/patches-4.0/205-arm_mvebu_enable_pwm_in_defconfig.patch trunk/target/linux/mvebu/patches-4.0/207-armada-385-rd-mtd-partitions.patch trunk/target/linux/mvebu/patches-4.0/208-ARM-mvebu-385-ap-Add-partitions.patch Log: mvebu: add Linux 4.0 support Signed-off-by: Imre Kaloz <[email protected]> Copied: trunk/target/linux/mvebu/config-4.0 (from rev 44528, trunk/target/linux/mvebu/config-3.19) =================================================================== --- trunk/target/linux/mvebu/config-4.0 (rev 0) +++ trunk/target/linux/mvebu/config-4.0 2015-03-19 10:25:44 UTC (rev 44882) @@ -0,0 +1,346 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MVEBU=y +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +CONFIG_ARMADA_370_CLK=y +CONFIG_ARMADA_370_XP_TIMER=y +CONFIG_ARMADA_38X_CLK=y +CONFIG_ARMADA_XP_CLK=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_MVEBU_V7_CPUIDLE=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BOUNCE=y +# CONFIG_CACHE_FEROCEON_L2 is not set +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PJ4B=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +# CONFIG_CPU_THERMAL is not set +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_XZ=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_MVEBU_UART=y +# CONFIG_DEBUG_MVEBU_UART_ALTERNATE is not set +CONFIG_DEBUG_UART_8250=y +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +CONFIG_DEBUG_UART_8250_SHIFT=2 +# CONFIG_DEBUG_UART_8250_WORD is not set +CONFIG_DEBUG_UART_PHYS=0xd0012000 +# CONFIG_DEBUG_UART_PL01X is not set +CONFIG_DEBUG_UART_VIRT=0xfec12000 +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_DEBUG_USER=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_OF=y +CONFIG_DTC=y +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_DW_DMAC_PCI is not set +CONFIG_EARLY_PRINTK=y +CONFIG_FIXED_PHY=y +CONFIG_FRAME_POINTER=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_MVEBU=y +CONFIG_GPIO_MVEBU_PWM=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_IWMMXT is not set +CONFIG_KERNFS=y +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACH_ARMADA_370=y +# CONFIG_MACH_ARMADA_375 is not set +CONFIG_MACH_ARMADA_38X=y +CONFIG_MACH_ARMADA_XP=y +# CONFIG_MACH_DOVE is not set +CONFIG_MACH_MVEBU_ANY=y +CONFIG_MACH_MVEBU_V7=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MEMORY=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_PXA3xx=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_SUPPORT=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UIMAGE_SPLIT=y +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_MVEBU_CLK_COMMON=y +CONFIG_MVEBU_CLK_COREDIV=y +CONFIG_MVEBU_CLK_CPU=y +CONFIG_MVEBU_DEVBUS=y +CONFIG_MVEBU_MBUS=y +CONFIG_MVMDIO=y +CONFIG_MVNETA=y +CONFIG_MVSW61XX_PHY=y +CONFIG_MV_XOR=y +CONFIG_NEED_DMA_MAP_STATE=y +# CONFIG_NEON is not set +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NO_BOOTMEM=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MVEBU=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_370=y +CONFIG_PINCTRL_ARMADA_38X=y +CONFIG_PINCTRL_ARMADA_XP=y +CONFIG_PINCTRL_MVEBU=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_PL310_ERRATA_588369 is not set +# CONFIG_PL310_ERRATA_727915 is not set +# CONFIG_PL310_ERRATA_753970 is not set +# CONFIG_PL310_ERRATA_769419 is not set +CONFIG_PLAT_ORION=y +CONFIG_PM_OPP=y +CONFIG_PWM=y +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PREEMPT_RCU is not set +CONFIG_RCU_STALL_COMMON=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_MV is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_8250_DW=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOC_BUS=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_ORION=y +CONFIG_STOP_MACHINE=y +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_STATS=y +CONFIG_TREE_RCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_XZ=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_VFPv3=y +# CONFIG_XEN is not set +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 Modified: trunk/target/linux/mvebu/patches-4.0/001-build_mamba_dts.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/001-build_mamba_dts.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/001-build_mamba_dts.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -1,6 +1,6 @@ --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile -@@ -541,6 +541,7 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \ +@@ -629,6 +629,7 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-db.dtb \ armada-xp-gp.dtb \ armada-xp-lenovo-ix4-300d.dtb \ Deleted: trunk/target/linux/mvebu/patches-4.0/019-mtd-nand-pxa3xx-Fix-PIO-FIFO-draining.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/019-mtd-nand-pxa3xx-Fix-PIO-FIFO-draining.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/019-mtd-nand-pxa3xx-Fix-PIO-FIFO-draining.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -1,97 +0,0 @@ -From 11aa9df4de06cc257327d783c5cb615989e87286 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard <[email protected]> -Date: Fri, 23 Jan 2015 15:18:27 +0100 -Subject: [PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining - -The NDDB register holds the data that are needed by the read and write -commands. - -However, during a read PIO access, the datasheet specifies that after each 32 -bits read in that register, when BCH is enabled, we have to make sure that the -RDDREQ bit is set in the NDSR register. - -This fixes an issue that was seen on the Armada 385, and presumably other mvebu -SoCs, when a read on a newly erased page would end up in the driver reporting a -timeout from the NAND. - -Cc: <[email protected]> # v3.14 -Signed-off-by: Maxime Ripard <[email protected]> ---- - drivers/mtd/nand/pxa3xx_nand.c | 45 ++++++++++++++++++++++++++++++++++++------ - 1 file changed, 39 insertions(+), 6 deletions(-) - -diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c -index 96b0b1d27df1..e6918befb951 100644 ---- a/drivers/mtd/nand/pxa3xx_nand.c -+++ b/drivers/mtd/nand/pxa3xx_nand.c -@@ -23,6 +23,7 @@ - #include <linux/mtd/partitions.h> - #include <linux/io.h> - #include <linux/irq.h> -+#include <linux/jiffies.h> - #include <linux/slab.h> - #include <linux/of.h> - #include <linux/of_device.h> -@@ -480,6 +481,38 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) - nand_writel(info, NDCR, ndcr | int_mask); - } - -+static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) -+{ -+ u32 *dst = (u32 *)data; -+ -+ if (info->ecc_bch) { -+ while (len--) { -+ u32 timeout; -+ -+ *dst++ = nand_readl(info, NDDB); -+ -+ /* -+ * According to the datasheet, when reading -+ * from NDDB with BCH enabled, after each 32 -+ * bits reads, we have to make sure that the -+ * NDSR.RDDREQ bit is set -+ */ -+ timeout = jiffies + msecs_to_jiffies(5); -+ while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) { -+ if (!time_before(jiffies, timeout)) { -+ dev_err(&info->pdev->dev, -+ "Timeout on RDDREQ while draining the FIFO\n"); -+ return; -+ } -+ -+ cpu_relax(); -+ } -+ } -+ } else { -+ __raw_readsl(info->mmio_base + NDDB, data, len); -+ } -+} -+ - static void handle_data_pio(struct pxa3xx_nand_info *info) - { - unsigned int do_bytes = min(info->data_size, info->chunk_size); -@@ -496,14 +529,14 @@ static void handle_data_pio(struct pxa3xx_nand_info *info) - DIV_ROUND_UP(info->oob_size, 4)); - break; - case STATE_PIO_READING: -- __raw_readsl(info->mmio_base + NDDB, -- info->data_buff + info->data_buff_pos, -- DIV_ROUND_UP(do_bytes, 4)); -+ drain_fifo(info, -+ info->data_buff + info->data_buff_pos, -+ DIV_ROUND_UP(do_bytes, 4)); - - if (info->oob_size > 0) -- __raw_readsl(info->mmio_base + NDDB, -- info->oob_buff + info->oob_buff_pos, -- DIV_ROUND_UP(info->oob_size, 4)); -+ drain_fifo(info, -+ info->oob_buff + info->oob_buff_pos, -+ DIV_ROUND_UP(info->oob_size, 4)); - break; - default: - dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, --- -2.2.2 - Deleted: trunk/target/linux/mvebu/patches-4.0/020-ARM-mvebu-Add-a-number-of-pinctrl-functions.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/020-ARM-mvebu-Add-a-number-of-pinctrl-functions.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/020-ARM-mvebu-Add-a-number-of-pinctrl-functions.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -1,70 +0,0 @@ -From 91b4c91f919abffa72cbf7545a944252f8e4f775 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard <[email protected]> -Date: Thu, 8 Jan 2015 18:38:08 +0100 -Subject: [PATCH 3/4] ARM: mvebu: Add a number of pinctrl functions - -Some pinctrl functions can be shared with all DTS out there, since they are -generic, SoC-wide muxing options. Add a number of these to the DTSI to avoid -duplication. - -Signed-off-by: Maxime Ripard <[email protected]> -Acked-by: Gregory CLEMENT <[email protected]> -Signed-off-by: Gregory CLEMENT <[email protected]> -Signed-off-by: Andrew Lunn <[email protected]> ---- - arch/arm/boot/dts/armada-38x.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ - 1 file changed, 39 insertions(+) - -diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi -index 40200084c6c8..98885c58be29 100644 ---- a/arch/arm/boot/dts/armada-38x.dtsi -+++ b/arch/arm/boot/dts/armada-38x.dtsi -@@ -195,6 +195,45 @@ - - pinctrl@18000 { - reg = <0x18000 0x20>; -+ -+ ge0_rgmii_pins: ge-rgmii-pins-0 { -+ marvell,pins = "mpp6", "mpp7", "mpp8", -+ "mpp9", "mpp10", "mpp11", -+ "mpp12", "mpp13", "mpp14", -+ "mpp15", "mpp16", "mpp17"; -+ marvell,function = "ge0"; -+ }; -+ -+ i2c0_pins: i2c-pins-0 { -+ marvell,pins = "mpp2", "mpp3"; -+ marvell,function = "i2c0"; -+ }; -+ -+ mdio_pins: mdio-pins { -+ marvell,pins = "mpp4", "mpp5"; -+ marvell,function = "ge"; -+ }; -+ -+ ref_clk0_pins: ref-clk-pins-0 { -+ marvell,pins = "mpp45"; -+ marvell,function = "ref"; -+ }; -+ -+ spi1_pins: spi-pins-1 { -+ marvell,pins = "mpp56", "mpp57", "mpp58", -+ "mpp59"; -+ marvell,function = "spi1"; -+ }; -+ -+ uart0_pins: uart-pins-0 { -+ marvell,pins = "mpp0", "mpp1"; -+ marvell,function = "ua0"; -+ }; -+ -+ uart1_pins: uart-pins-1 { -+ marvell,pins = "mpp19", "mpp20"; -+ marvell,function = "ua1"; -+ }; - }; - - gpio0: gpio@18100 { --- -2.2.1 - Deleted: trunk/target/linux/mvebu/patches-4.0/021-ARM-mvebu-Add-Armada-385-Access-Point-Development-Bo.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/021-ARM-mvebu-Add-Armada-385-Access-Point-Development-Bo.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/021-ARM-mvebu-Add-Armada-385-Access-Point-Development-Bo.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -1,220 +0,0 @@ -From e5ee12817e9eac891c6b2a340f64d94d9abd355f Mon Sep 17 00:00:00 2001 -From: Maxime Ripard <[email protected]> -Date: Thu, 8 Jan 2015 18:38:09 +0100 -Subject: [PATCH 4/4] ARM: mvebu: Add Armada 385 Access Point Development Board - support - -The A385-AP is a board produced by Marvell that holds 3 mPCIe slot, a 16MB -SPI-NOR, 3 Gigabit Ethernet ports, USB3 and NAND flash storage. - -[[email protected]: switch the license to the dual -X11/GPL with the agreement of the author] - -Signed-off-by: Maxime Ripard <[email protected]> -Signed-off-by: Gregory CLEMENT <[email protected]> -Signed-off-by: Andrew Lunn <[email protected]> ---- - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/armada-385-db-ap.dts | 178 +++++++++++++++++++++++++++++++++ - 2 files changed, 179 insertions(+) - create mode 100644 arch/arm/boot/dts/armada-385-db-ap.dts - -diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile -index 6dc9c17f9ff5..d34837104949 100644 ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -536,6 +536,7 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \ - armada-375-db.dtb - dtb-$(CONFIG_MACH_ARMADA_38X) += \ - armada-385-db.dtb \ -+ armada-385-db-ap.dtb \ - armada-385-rd.dtb - dtb-$(CONFIG_MACH_ARMADA_XP) += \ - armada-xp-axpwifiap.dtb \ -diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts -new file mode 100644 -index 000000000000..57b9119fb3e0 ---- /dev/null -+++ b/arch/arm/boot/dts/armada-385-db-ap.dts -@@ -0,0 +1,178 @@ -+/* -+ * Device Tree file for Marvell Armada 385 Access Point Development board -+ * (DB-88F6820-AP) -+ * -+ * Copyright (C) 2014 Marvell -+ * -+ * Nadav Haklai <[email protected]> -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without -+ * any warranty of any kind, whether express or implied. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+#include "armada-385.dtsi" -+ -+#include <dt-bindings/gpio/gpio.h> -+ -+/ { -+ model = "Marvell Armada 385 Access Point Development Board"; -+ compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x"; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200"; -+ stdout-path = &uart1; -+ }; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x00000000 0x80000000>; /* 2GB */ -+ }; -+ -+ soc { -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 -+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; -+ -+ internal-regs { -+ spi1: spi@10680 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+ status = "okay"; -+ -+ spi-flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p128"; -+ reg = <0>; /* Chip select 0 */ -+ spi-max-frequency = <54000000>; -+ }; -+ }; -+ -+ i2c0: i2c@11000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ status = "okay"; -+ -+ /* -+ * This bus is wired to two EEPROM -+ * sockets, one of which holding the -+ * board ID used by the bootloader. -+ * Erasing this EEPROM's content will -+ * brick the board. -+ * Use this bus with caution. -+ */ -+ }; -+ -+ mdio@72004 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mdio_pins>; -+ -+ phy0: ethernet-phy@1 { -+ reg = <1>; -+ }; -+ -+ phy1: ethernet-phy@4 { -+ reg = <4>; -+ }; -+ -+ phy2: ethernet-phy@6 { -+ reg = <6>; -+ }; -+ }; -+ -+ /* UART0 is exposed through the JP8 connector */ -+ uart0: serial@12000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+ status = "okay"; -+ }; -+ -+ /* -+ * UART1 is exposed through a FTDI chip -+ * wired to the mini-USB connector -+ */ -+ uart1: serial@12100 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+ status = "okay"; -+ }; -+ -+ ethernet@30000 { -+ status = "okay"; -+ phy = <&phy2>; -+ phy-mode = "sgmii"; -+ }; -+ -+ ethernet@34000 { -+ status = "okay"; -+ phy = <&phy1>; -+ phy-mode = "sgmii"; -+ }; -+ -+ ethernet@70000 { -+ pinctrl-names = "default"; -+ -+ /* -+ * The Reference Clock 0 is used to -+ * provide a clock to the PHY -+ */ -+ pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; -+ status = "okay"; -+ phy = <&phy0>; -+ phy-mode = "rgmii-id"; -+ }; -+ }; -+ -+ pcie-controller { -+ status = "okay"; -+ -+ /* -+ * The three PCIe units are accessible through -+ * standard mini-PCIe slots on the board. -+ */ -+ pcie@1,0 { -+ /* Port 0, Lane 0 */ -+ status = "okay"; -+ }; -+ -+ pcie@2,0 { -+ /* Port 1, Lane 0 */ -+ status = "okay"; -+ }; -+ -+ pcie@3,0 { -+ /* Port 2, Lane 0 */ -+ status = "okay"; -+ }; -+ }; -+ }; -+}; --- -2.2.1 - Modified: trunk/target/linux/mvebu/patches-4.0/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -10,11 +10,9 @@ arch/arm/boot/dts/armada-385-db-ap.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) -diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts -index 3a51531eb37b..02db04867d8f 100644 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ b/arch/arm/boot/dts/armada-385-db-ap.dts -@@ -122,6 +122,19 @@ +@@ -150,6 +150,19 @@ phy = <&phy0>; phy-mode = "rgmii-id"; }; @@ -34,6 +32,3 @@ }; pcie-controller { --- -2.2.1 - Deleted: trunk/target/linux/mvebu/patches-4.0/023-pinctrl-mvebu-a38x-Add-UART1-muxing-options.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/023-pinctrl-mvebu-a38x-Add-UART1-muxing-options.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/023-pinctrl-mvebu-a38x-Add-UART1-muxing-options.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -1,43 +0,0 @@ -From a95308d88c07e0093aedae7e64f92cb1e165f592 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard <[email protected]> -Date: Fri, 5 Dec 2014 15:44:57 +0100 -Subject: [PATCH] pinctrl: mvebu: a38x: Add UART1 muxing options - -The MPP19 and MMP20 pins also have the ability to be muxed to the uart1 -function. - -Add this case to the pinctrl driver. - -Signed-off-by: Maxime Ripard <[email protected]> -Acked-by: Jason Cooper <[email protected]> -Signed-off-by: Linus Walleij <[email protected]> ---- - drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c -index 224c6cff6aa2..7302f66f4f19 100644 ---- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c -+++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c -@@ -145,14 +145,16 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { - MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "pcie0", "clkreq", V_88F6810_PLUS), - MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS), -- MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS)), -+ MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS), -+ MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)), - MPP_MODE(20, - MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), - MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), - MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS), -- MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS)), -+ MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS), -+ MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)), - MPP_MODE(21, - MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), - MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6810_PLUS), --- -2.2.1 - Deleted: trunk/target/linux/mvebu/patches-4.0/024-ARM-mvebu-a38x-Fix-node-names.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/024-ARM-mvebu-a38x-Fix-node-names.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/024-ARM-mvebu-a38x-Fix-node-names.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -1,98 +0,0 @@ -From 4a25432b13090b57d257fa0ffb6712d8acf94523 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard <[email protected]> -Date: Thu, 8 Jan 2015 18:38:05 +0100 -Subject: [PATCH 1/4] ARM: mvebu: a38x: Fix node names - -Some nodes in the DTs have a reg property but no unit name in their node name. - -This contradicts the way the ePAPR defines the node names. Fix this. - -Signed-off-by: Maxime Ripard <[email protected]> -Acked-by: Gregory CLEMENT <[email protected]> -Signed-off-by: Gregory CLEMENT <[email protected]> -Signed-off-by: Andrew Lunn <[email protected]> ---- - arch/arm/boot/dts/armada-380.dtsi | 2 +- - arch/arm/boot/dts/armada-385-db.dts | 2 +- - arch/arm/boot/dts/armada-385-rd.dts | 2 +- - arch/arm/boot/dts/armada-385.dtsi | 2 +- - arch/arm/boot/dts/armada-38x.dtsi | 4 ++-- - 5 files changed, 6 insertions(+), 6 deletions(-) - -diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi -index 4173a8ab34e7..13400ce88c54 100644 ---- a/arch/arm/boot/dts/armada-380.dtsi -+++ b/arch/arm/boot/dts/armada-380.dtsi -@@ -32,7 +32,7 @@ - - soc { - internal-regs { -- pinctrl { -+ pinctrl@18000 { - compatible = "marvell,mv88f6810-pinctrl"; - reg = <0x18000 0x20>; - }; -diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts -index 2aaa9d2ac284..212605ccc7b6 100644 ---- a/arch/arm/boot/dts/armada-385-db.dts -+++ b/arch/arm/boot/dts/armada-385-db.dts -@@ -74,7 +74,7 @@ - phy-mode = "rgmii-id"; - }; - -- mdio { -+ mdio@72004 { - phy0: ethernet-phy@0 { - reg = <0>; - }; -diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts -index aaca2861dc87..74a3bfe6efd7 100644 ---- a/arch/arm/boot/dts/armada-385-rd.dts -+++ b/arch/arm/boot/dts/armada-385-rd.dts -@@ -67,7 +67,7 @@ - }; - - -- mdio { -+ mdio@72004 { - phy0: ethernet-phy@0 { - reg = <0>; - }; -diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi -index 6283d7912f71..5249a4d3c207 100644 ---- a/arch/arm/boot/dts/armada-385.dtsi -+++ b/arch/arm/boot/dts/armada-385.dtsi -@@ -37,7 +37,7 @@ - - soc { - internal-regs { -- pinctrl { -+ pinctrl@18000 { - compatible = "marvell,mv88f6820-pinctrl"; - reg = <0x18000 0x20>; - }; -diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi -index 74391dace9e7..ada1f206028b 100644 ---- a/arch/arm/boot/dts/armada-38x.dtsi -+++ b/arch/arm/boot/dts/armada-38x.dtsi -@@ -193,7 +193,7 @@ - status = "disabled"; - }; - -- pinctrl { -+ pinctrl@18000 { - compatible = "marvell,mv88f6820-pinctrl"; - reg = <0x18000 0x20>; - }; -@@ -373,7 +373,7 @@ - status = "disabled"; - }; - -- mdio { -+ mdio@72004 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; --- -2.2.1 - Modified: trunk/target/linux/mvebu/patches-4.0/051-leds_tlc59116_add_driver.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/051-leds_tlc59116_add_driver.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/051-leds_tlc59116_add_driver.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -15,7 +15,7 @@ --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -457,6 +457,14 @@ config LEDS_TCA6507 +@@ -467,6 +467,14 @@ config LEDS_TCA6507 LED driver chips accessed via the I2C bus. Driver support brightness control and hardware-assisted blinking. @@ -32,7 +32,7 @@ depends on LEDS_CLASS && MFD_MAX8997 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile -@@ -30,6 +30,7 @@ obj-$(CONFIG_LEDS_LP8501) += leds-lp850 +@@ -31,6 +31,7 @@ obj-$(CONFIG_LEDS_LP8501) += leds-lp850 obj-$(CONFIG_LEDS_LP8788) += leds-lp8788.o obj-$(CONFIG_LEDS_LP8860) += leds-lp8860.o obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o Modified: trunk/target/linux/mvebu/patches-4.0/102-revert_i2c_delay.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/102-revert_i2c_delay.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/102-revert_i2c_delay.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -1,6 +1,6 @@ --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi -@@ -54,12 +54,10 @@ +@@ -88,12 +88,10 @@ }; i2c0: i2c@11000 { Deleted: trunk/target/linux/mvebu/patches-4.0/200-gpio_mvebu_checkpatch_fixes.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/200-gpio_mvebu_checkpatch_fixes.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/200-gpio_mvebu_checkpatch_fixes.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -1,223 +0,0 @@ -Wrap some long lines. -Prefer seq_puts() over seq_printf(). -space to tab conversions. -Spelling error fix. - -Signed-off-by: Andrew Lunn <[email protected]> ---- - drivers/gpio/gpio-mvebu.c | 77 ++++++++++++++++++++++++++--------------------- - 1 file changed, 42 insertions(+), 35 deletions(-) - ---- a/drivers/gpio/gpio-mvebu.c -+++ b/drivers/gpio/gpio-mvebu.c -@@ -59,7 +59,7 @@ - #define GPIO_LEVEL_MASK_OFF 0x001c - - /* The MV78200 has per-CPU registers for edge mask and level mask */ --#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) -+#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) - #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) - - /* The Armada XP has per-CPU registers for interrupt cause, interrupt -@@ -69,11 +69,11 @@ - #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) - #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) - --#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 --#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 -+#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 -+#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 - #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 - --#define MVEBU_MAX_GPIO_PER_BANK 32 -+#define MVEBU_MAX_GPIO_PER_BANK 32 - - struct mvebu_gpio_chip { - struct gpio_chip chip; -@@ -82,9 +82,9 @@ struct mvebu_gpio_chip { - void __iomem *percpu_membase; - int irqbase; - struct irq_domain *domain; -- int soc_variant; -+ int soc_variant; - -- /* Used to preserve GPIO registers accross suspend/resume */ -+ /* Used to preserve GPIO registers across suspend/resume */ - u32 out_reg; - u32 io_conf_reg; - u32 blink_en_reg; -@@ -107,7 +107,8 @@ static inline void __iomem *mvebu_gpiore - return mvchip->membase + GPIO_BLINK_EN_OFF; - } - --static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) -+static inline void __iomem * -+mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) - { - return mvchip->membase + GPIO_IO_CONF_OFF; - } -@@ -117,12 +118,14 @@ static inline void __iomem *mvebu_gpiore - return mvchip->membase + GPIO_IN_POL_OFF; - } - --static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) -+static inline void __iomem * -+mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) - { - return mvchip->membase + GPIO_DATA_IN_OFF; - } - --static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) -+static inline void __iomem * -+mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) - { - int cpu; - -@@ -132,13 +135,15 @@ static inline void __iomem *mvebu_gpiore - return mvchip->membase + GPIO_EDGE_CAUSE_OFF; - case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: - cpu = smp_processor_id(); -- return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); -+ return mvchip->percpu_membase + -+ GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); - default: - BUG(); - } - } - --static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) -+static inline void __iomem * -+mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) - { - int cpu; - -@@ -150,7 +155,8 @@ static inline void __iomem *mvebu_gpiore - return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); - case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: - cpu = smp_processor_id(); -- return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); -+ return mvchip->percpu_membase + -+ GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); - default: - BUG(); - } -@@ -168,7 +174,8 @@ static void __iomem *mvebu_gpioreg_level - return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu); - case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: - cpu = smp_processor_id(); -- return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); -+ return mvchip->percpu_membase + -+ GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); - default: - BUG(); - } -@@ -364,22 +371,22 @@ static void mvebu_gpio_level_irq_unmask( - * value of the line or the opposite value. - * - * Level IRQ handlers: DATA_IN is used directly as cause register. -- * Interrupt are masked by LEVEL_MASK registers. -+ * Interrupt are masked by LEVEL_MASK registers. - * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. -- * Interrupt are masked by EDGE_MASK registers. -+ * Interrupt are masked by EDGE_MASK registers. - * Both-edge handlers: Similar to regular Edge handlers, but also swaps -- * the polarity to catch the next line transaction. -- * This is a race condition that might not perfectly -- * work on some use cases. -+ * the polarity to catch the next line transaction. -+ * This is a race condition that might not perfectly -+ * work on some use cases. - * - * Every eight GPIO lines are grouped (OR'ed) before going up to main - * cause register. - * -- * EDGE cause mask -- * data-in /--------| |-----| |----\ -- * -----| |----- ---- to main cause reg -- * X \----------------| |----/ -- * polarity LEVEL mask -+ * EDGE cause mask -+ * data-in /--------| |-----| |----\ -+ * -----| |----- ---- to main cause reg -+ * X \----------------| |----/ -+ * polarity LEVEL mask - * - ****************************************************************************/ - -@@ -394,9 +401,8 @@ static int mvebu_gpio_irq_set_type(struc - pin = d->hwirq; - - u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin); -- if (!u) { -+ if (!u) - return -EINVAL; -- } - - type &= IRQ_TYPE_SENSE_MASK; - if (type == IRQ_TYPE_NONE) -@@ -529,13 +535,13 @@ static void mvebu_gpio_dbg_show(struct s - (data_in ^ in_pol) & msk ? "hi" : "lo", - in_pol & msk ? "lo" : "hi"); - if (!((edg_msk | lvl_msk) & msk)) { -- seq_printf(s, " disabled\n"); -+ seq_puts(s, " disabled\n"); - continue; - } - if (edg_msk & msk) -- seq_printf(s, " edge "); -+ seq_puts(s, " edge "); - if (lvl_msk & msk) -- seq_printf(s, " level"); -+ seq_puts(s, " level"); - seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); - } - } -@@ -546,15 +552,15 @@ static void mvebu_gpio_dbg_show(struct s - static const struct of_device_id mvebu_gpio_of_match[] = { - { - .compatible = "marvell,orion-gpio", -- .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, -+ .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, - }, - { - .compatible = "marvell,mv78200-gpio", -- .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, -+ .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, - }, - { - .compatible = "marvell,armadaxp-gpio", -- .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, -+ .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, - }, - { - /* sentinel */ -@@ -668,7 +674,8 @@ static int mvebu_gpio_probe(struct platf - else - soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; - -- mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL); -+ mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), -+ GFP_KERNEL); - if (!mvchip) - return -ENOMEM; - -@@ -767,8 +774,8 @@ static int mvebu_gpio_probe(struct platf - * interrupt handlers, with each handler dealing with 8 GPIO - * pins. */ - for (i = 0; i < 4; i++) { -- int irq; -- irq = platform_get_irq(pdev, i); -+ int irq = platform_get_irq(pdev, i); -+ - if (irq < 0) - continue; - irq_set_handler_data(irq, mvchip); -@@ -827,7 +834,7 @@ static int mvebu_gpio_probe(struct platf - - static struct platform_driver mvebu_gpio_driver = { - .driver = { -- .name = "mvebu-gpio", -+ .name = "mvebu-gpio", - .of_match_table = mvebu_gpio_of_match, - }, - .probe = mvebu_gpio_probe, Deleted: trunk/target/linux/mvebu/patches-4.0/201-gpio_mvebu_fix_probe_cleanup_on_error.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/201-gpio_mvebu_fix_probe_cleanup_on_error.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/201-gpio_mvebu_fix_probe_cleanup_on_error.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -1,63 +0,0 @@ -Ensure that when there is an error during probe that the gpiochip is -removed and the generic irq chip is removed. - -Signed-off-by: Andrew Lunn <[email protected]> ---- - drivers/gpio/gpio-mvebu.c | 23 +++++++++++++++++------ - 1 file changed, 17 insertions(+), 6 deletions(-) - ---- a/drivers/gpio/gpio-mvebu.c -+++ b/drivers/gpio/gpio-mvebu.c -@@ -667,6 +667,7 @@ static int mvebu_gpio_probe(struct platf - unsigned int ngpios; - int soc_variant; - int i, cpu, id; -+ int err; - - match = of_match_device(mvebu_gpio_of_match, &pdev->dev); - if (match) -@@ -785,14 +786,16 @@ static int mvebu_gpio_probe(struct platf - mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1); - if (mvchip->irqbase < 0) { - dev_err(&pdev->dev, "no irqs\n"); -- return mvchip->irqbase; -+ err = mvchip->irqbase; -+ goto err_gpiochip_add; - } - - gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase, - mvchip->membase, handle_level_irq); - if (!gc) { - dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n"); -- return -ENOMEM; -+ err = -ENOMEM; -+ goto err_gpiochip_add; - } - - gc->private = mvchip; -@@ -823,13 +826,21 @@ static int mvebu_gpio_probe(struct platf - if (!mvchip->domain) { - dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", - mvchip->chip.label); -- irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, -- IRQ_LEVEL | IRQ_NOPROBE); -- kfree(gc); -- return -ENODEV; -+ err = -ENODEV; -+ goto err_generic_chip; - } - - return 0; -+ -+err_generic_chip: -+ irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, -+ IRQ_LEVEL | IRQ_NOPROBE); -+ kfree(gc); -+ -+err_gpiochip_add: -+ gpiochip_remove(&mvchip->chip); -+ -+ return err; - } - - static struct platform_driver mvebu_gpio_driver = { Modified: trunk/target/linux/mvebu/patches-4.0/202-gpio_mvebu_add_limited_pwm_support.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/202-gpio_mvebu_add_limited_pwm_support.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/202-gpio_mvebu_add_limited_pwm_support.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -23,7 +23,7 @@ --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig -@@ -239,6 +239,11 @@ config GPIO_MVEBU +@@ -246,6 +246,11 @@ config GPIO_MVEBU select GPIO_GENERIC select GENERIC_IRQ_CHIP @@ -37,7 +37,7 @@ depends on ARCH_MXC --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile -@@ -60,6 +60,7 @@ obj-$(CONFIG_GPIO_MSIC) += gpio-msic.o +@@ -61,6 +61,7 @@ obj-$(CONFIG_GPIO_MSIC) += gpio-msic.o obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o Modified: trunk/target/linux/mvebu/patches-4.0/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -11,7 +11,7 @@ --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi -@@ -123,24 +123,30 @@ +@@ -157,24 +157,30 @@ gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; @@ -46,7 +46,7 @@ gpio2: gpio@18180 { --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi -@@ -169,24 +169,30 @@ +@@ -203,24 +203,30 @@ internal-regs { gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; @@ -81,7 +81,7 @@ }; --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi -@@ -253,24 +253,28 @@ +@@ -287,24 +287,28 @@ internal-regs { gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; @@ -114,7 +114,7 @@ gpio2: gpio@18180 { --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi -@@ -291,24 +291,30 @@ +@@ -325,24 +325,30 @@ internal-regs { gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; Modified: trunk/target/linux/mvebu/patches-4.0/205-arm_mvebu_enable_pwm_in_defconfig.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/205-arm_mvebu_enable_pwm_in_defconfig.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/205-arm_mvebu_enable_pwm_in_defconfig.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -8,7 +8,7 @@ --- a/arch/arm/configs/mvebu_v7_defconfig +++ b/arch/arm/configs/mvebu_v7_defconfig -@@ -116,6 +116,7 @@ CONFIG_DMADEVICES=y +@@ -118,6 +118,7 @@ CONFIG_DMADEVICES=y CONFIG_MV_XOR=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_MEMORY=y Modified: trunk/target/linux/mvebu/patches-4.0/207-armada-385-rd-mtd-partitions.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/207-armada-385-rd-mtd-partitions.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/207-armada-385-rd-mtd-partitions.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -1,6 +1,6 @@ ---- a/arch/arm/boot/dts/armada-385-rd.dts -+++ b/arch/arm/boot/dts/armada-385-rd.dts -@@ -42,6 +42,16 @@ +--- a/arch/arm/boot/dts/armada-388-rd.dts ++++ b/arch/arm/boot/dts/armada-388-rd.dts +@@ -77,6 +77,16 @@ compatible = "st,m25p128"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <108000000>; Modified: trunk/target/linux/mvebu/patches-4.0/208-ARM-mvebu-385-ap-Add-partitions.patch =================================================================== --- trunk/target/linux/mvebu/patches-3.19/208-ARM-mvebu-385-ap-Add-partitions.patch 2015-02-24 12:01:08 UTC (rev 44528) +++ trunk/target/linux/mvebu/patches-4.0/208-ARM-mvebu-385-ap-Add-partitions.patch 2015-03-19 10:25:44 UTC (rev 44882) @@ -8,11 +8,9 @@ arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts -index 02db04867d8f..2a58443e2504 100644 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ b/arch/arm/boot/dts/armada-385-db-ap.dts -@@ -134,6 +134,21 @@ +@@ -162,6 +162,21 @@ marvell,nand-keep-config; marvell,nand-enable-arbiter; nand-on-flash-bbt; @@ -34,6 +32,3 @@ }; }; --- -2.2.1 - _______________________________________________ openwrt-commits mailing list [email protected] https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-commits
