Author: nbd Date: 2015-04-20 17:00:20 +0200 (Mon, 20 Apr 2015) New Revision: 45521
Modified: trunk/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c Log: ar71xx: Remove TX/RX delay from pll_1000 for OM5P-AN The tx/rx delay bits in the ETH_XMII_CONTROL register have to be unset when the enable_rgmii_rx_delay/enable_rgmii_tx_delay will be set in the AT803x PHY. Othwise the throughput in gigabit mode is heavily reduced. Signed-off-by: Sven Eckelmann <[email protected]> Modified: trunk/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c =================================================================== --- trunk/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c 2015-04-20 15:00:13 UTC (rev 45520) +++ trunk/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c 2015-04-20 15:00:20 UTC (rev 45521) @@ -202,7 +202,7 @@ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_data.phy_mask = BIT(7); - ath79_eth0_pll_data.pll_1000 = 0x1a000000; + ath79_eth0_pll_data.pll_1000 = 0x02000000; ath79_eth0_pll_data.pll_100 = 0x00000101; ath79_eth0_pll_data.pll_10 = 0x00001313; ath79_register_eth(0); _______________________________________________ openwrt-commits mailing list [email protected] https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-commits
