Author: blogic Date: 2015-09-16 10:33:04 +0200 (Wed, 16 Sep 2015) New Revision: 46971
Modified: trunk/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c Log: ath79: dev-eth: fix QCA9561 set phy interface mode and mask QCA9563 and QCA9561 are two series of Qualcomm SoC Dragonfly. The only different is QCA9563 w/o internal switch. It has one GMAC with SGMII interface. But they have the same device ID(0x1150). So they share the same codes. Signed-off-by: Miaoqing Pan <[email protected]> Modified: trunk/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c =================================================================== --- trunk/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c 2015-09-16 08:32:56 UTC (rev 46970) +++ trunk/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c 2015-09-16 08:33:04 UTC (rev 46971) @@ -633,7 +633,6 @@ case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: case ATH79_SOC_QCA9533: - case ATH79_SOC_QCA9561: case ATH79_SOC_TP9343: pdata->phy_if_mode = PHY_INTERFACE_MODE_MII; break; @@ -667,6 +666,11 @@ } break; + case ATH79_SOC_QCA9561: + if (!pdata->phy_if_mode) + pdata->phy_if_mode = PHY_INTERFACE_MODE_MII; + break; + default: BUG(); } @@ -1035,7 +1039,8 @@ AR933X_RESET_GE0_MDIO; pdata->set_speed = ath79_set_speed_dummy; - pdata->phy_mask = BIT(4); + if (!pdata->phy_mask) + pdata->phy_mask = BIT(4); } else { pdata->reset_bit = AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO; _______________________________________________ openwrt-commits mailing list [email protected] https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-commits
