Author: blogic Date: 2016-03-16 10:27:04 +0100 (Wed, 16 Mar 2016) New Revision: 49028
Modified: trunk/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c Log: ar71xx: Clear bits in ath79_setup_qca955x_eth_cfg Some u-boot versions for QCA955x set currently not cleared bits depending on the used link speed. This breaks the rx/tx under OpenWrt. The mach-*.c file is responsible to select the correct configuration bits and thus the ath79_setup_qca955x_eth_cfg has to clear the unset. Signed-off-by: Sven Eckelmann <[email protected]> Modified: trunk/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c =================================================================== --- trunk/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c 2016-03-16 09:27:01 UTC (rev 49027) +++ trunk/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c 2016-03-16 09:27:04 UTC (rev 49028) @@ -833,14 +833,24 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask) { void __iomem *base; - u32 t; + u32 t, m; + m = QCA955X_ETH_CFG_RGMII_EN | + QCA955X_ETH_CFG_MII_GE0 | + QCA955X_ETH_CFG_GMII_GE0 | + QCA955X_ETH_CFG_MII_GE0_MASTER | + QCA955X_ETH_CFG_MII_GE0_SLAVE | + QCA955X_ETH_CFG_GE0_ERR_EN | + QCA955X_ETH_CFG_GE0_SGMII | + QCA955X_ETH_CFG_RMII_GE0 | + QCA955X_ETH_CFG_MII_CNTL_SPEED | + QCA955X_ETH_CFG_RMII_GE0_MASTER; + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG); - t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII); - + t &= ~m; t |= mask; __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); _______________________________________________ openwrt-commits mailing list [email protected] https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-commits
