This basically selects the new generic MIPS timer code for BCM963xx and
kickstarts the C0 compare IRQ when initializing the timer.
Signed-off-by: Axel Gembe <[EMAIL PROTECTED]>
---
.../patches/070-bcm963xx_add_new_timer_code.patch | 46 ++++++++++++++++++++
1 files changed, 46 insertions(+), 0 deletions(-)
create mode 100644
target/linux/brcm63xx/patches/070-bcm963xx_add_new_timer_code.patch
diff --git
a/target/linux/brcm63xx/patches/070-bcm963xx_add_new_timer_code.patch
b/target/linux/brcm63xx/patches/070-bcm963xx_add_new_timer_code.patch
new file mode 100644
index 0000000..3e1c2b0
--- /dev/null
+++ b/target/linux/brcm63xx/patches/070-bcm963xx_add_new_timer_code.patch
@@ -0,0 +1,46 @@
+From 89c4ca5f7158b21b4609593b61b48a33b736aa53 Mon Sep 17 00:00:00 2001
+From: Axel Gembe <[EMAIL PROTECTED]>
+Date: Mon, 12 May 2008 21:43:02 +0200
+Subject: [PATCH 6/8] bcm963xx: add new timer code
+
+This basically selects the new generic MIPS timer code for BCM963xx and
+kickstarts the C0 compare IRQ when initializing the timer.
+
+Signed-off-by: Axel Gembe <[EMAIL PROTECTED]>
+---
+ arch/mips/Kconfig | 2 ++
+ arch/mips/bcm963xx/time.c | 7 +++++++
+ 2 files changed, 9 insertions(+), 0 deletions(-)
+
+diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
+index 645158d..ee77f56 100644
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -75,6 +75,8 @@ config BCM963XX
+ select HW_HAS_PCI
+ select DMA_NONCOHERENT
+ select IRQ_CPU
++ select CEVT_R4K
++ select CSRC_R4K
+ help
+ This is a fmaily of boards based on the Broadcom MIPS32
+
+diff --git a/arch/mips/bcm963xx/time.c b/arch/mips/bcm963xx/time.c
+index 8a5007e..06a5f8c 100644
+--- a/arch/mips/bcm963xx/time.c
++++ b/arch/mips/bcm963xx/time.c
+@@ -86,4 +86,11 @@ void __init plat_time_init(void)
+ printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
+ (est_freq % 1000000) * 100 / 1000000);
+ local_irq_restore(flags);
++
++ /*
++ * Use deterministic values for initial counter interrupt
++ * so that calibrate delay avoids encountering a counter wrap.
++ */
++ write_c0_count(0);
++ write_c0_compare(0xffff);
+ }
+--
+1.5.5.1
+
--
1.5.5.1
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