On 03/22/2010 10:58 AM, Bas Mevissen wrote: > On Fri, 2010-03-19 at 16:56 +0100, Joerg Albert wrote: >> I looked closer at the PCB and it turned out that we have a voltage >> divider with two 5.6 kOhm to V_3_3 and GND (R613, R614) and a >> capacitor C496 (!) towards the CPU. The signal at the CPU looked fine >> for a 2.5V TTL. >> The voltage drift seen above is probably caused by the capacitor >> unloading when the CPU pin is driven down. >> > > Curious design choice. Works fine for continuous signals at higher > frequencies, but not here.
Yes. I sent an email to the manufacturer, just in case they do a redesign ;-) >> I removed the resitors and replaced C496 by a 1k resistor (to protect >> the CPU pin against shorts). This solved my problem. >> I guess the above schematics was meant to be a cheap TTL level >> conversion 2.5V -> 3.3V. >> >> Thanks for sending me again to the oscilloscope! > > I'm happy it is solved now. Maybe you can document this in relevant > places on the web. I couldn't find a page for the WR741ND in the OpenWRT wiki, so I guess I'll create one. Regards, Jörg. _______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/mailman/listinfo/openwrt-devel
