Here is SPI-bus implementation for ralink devices.
Index: target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c
===================================================================
--- target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c (revision 26927)
+++ target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c (working copy)
@@ -217,3 +217,24 @@
platform_device_register(&rt305x_wdt_device);
}
+
+static struct resource rt305x_spi_resources[] = {
+ {
+ .name = "spi-regs",
+ .flags = IORESOURCE_MEM,
+ .start = RT305X_SPI_BASE,
+ .end = RT305X_SPI_BASE + RT305X_SPI_SIZE - 1,
+ },
+};
+
+static struct platform_device rt305x_spi_device = {
+ .name = "ramips-spi",
+ .id = 0,
+ .resource = rt305x_spi_resources,
+ .num_resources = ARRAY_SIZE(rt305x_spi_resources),
+};
+
+void __init rt305x_register_spi(void)
+{
+ platform_device_register(&rt305x_spi_device);
+};
Index: target/linux/ramips/files/arch/mips/ralink/rt305x/devices.h
===================================================================
--- target/linux/ramips/files/arch/mips/ralink/rt305x/devices.h (revision 26927)
+++ target/linux/ramips/files/arch/mips/ralink/rt305x/devices.h (working copy)
@@ -21,6 +21,7 @@
void rt305x_register_ethernet(void);
void rt305x_register_wifi(void);
void rt305x_register_wdt(void);
+void rt305x_register_spi(void);
#endif /* __RT305X_DEVICES_H */
Index: target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_spi.h
===================================================================
--- target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_spi.h (revision 0)
+++ target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_spi.h (revision 0)
@@ -0,0 +1,45 @@
+/*
+ * SPI Controller
+ *
+ * Copyright (C) 2011 Sergiy <[email protected]>
+ *
+ * This code is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __RAMIPS_SPIFLASH_H
+#define __RAMIPS_SPIFLASH_H
+
+#define RAMIPS_SPI_STAT 0x00
+#define RAMIPS_SPI_CFG 0x10
+#define RAMIPS_SPI_CTL 0x14
+#define RAMIPS_SPI_DATA 0x20
+
+/* SPISTAT register bit field */
+#define SPISTAT_BUSY 0x00000001
+
+/* SPICFG register bit field */
+#define SPICFG_LSBFIRST (0<<8)
+#define SPICFG_MSBFIRST (1<<8)
+#define SPICFG_RXCLKEDGE_FALLING (1<<5) /* rx on the falling edge of the SPICLK signal */
+#define SPICFG_TXCLKEDGE_FALLING (1<<4) /* tx on the falling edge of the SPICLK signal */
+#define SPICFG_SPICLK_DIV2 (0<<0) /* system clock rate / 2 */
+#define SPICFG_SPICLK_DIV4 (1<<0) /* system clock rate / 4 */
+#define SPICFG_SPICLK_DIV8 (2<<0) /* system clock rate / 8 */
+#define SPICFG_SPICLK_DIV16 (3<<0) /* system clock rate / 16 */
+#define SPICFG_SPICLK_DIV32 (4<<0) /* system clock rate / 32 */
+#define SPICFG_SPICLK_DIV64 (5<<0) /* system clock rate / 64 */
+#define SPICFG_SPICLK_DIV128 (6<<0) /* system clock rate / 128 */
+#define SPICFG_SPICLK_DISABLE (7<<0) /* system clock disabled */
+#define SPICFG_SPICLKPOL (1<<6) /* spi clk*/
+
+/* SPICTL register bit field */
+#define SPICTL_HIZSDO (1<<3)
+#define SPICTL_STARTWR (1<<2)
+#define SPICTL_STARTRD (1<<1)
+#define SPICTL_SPIENA (1<<0)
+
+#define CFG_CLK_DIV SPICFG_SPICLK_DIV16
+
+#endif
Index: target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
===================================================================
--- target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h (revision 26927)
+++ target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h (working copy)
@@ -42,6 +42,7 @@
#define RT305X_UART0_SIZE 0x100
#define RT305X_PIO_SIZE 0x100
#define RT305X_UART1_SIZE 0x100
+#define RT305X_SPI_SIZE 0x100
#define RT305X_FLASH1_SIZE (16 * 1024 * 1024)
#define RT305X_FLASH0_SIZE (8 * 1024 * 1024)
Index: target/linux/ramips/files/drivers/spi/ramips_spi.c
===================================================================
--- target/linux/ramips/files/drivers/spi/ramips_spi.c (revision 0)
+++ target/linux/ramips/files/drivers/spi/ramips_spi.c (revision 0)
@@ -0,0 +1,524 @@
+/*
+ * ramips_spi.c -- Ralink RT288x/RT305x SPI controller driver
+ *
+ * Author: Sergiy <[email protected]>
+ * Copyright (C) 2011 OpenWrt.org.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/spi/spi.h>
+#include <asm/unaligned.h>
+
+
+#if defined(CONFIG_RALINK_RT305X)
+#include <rt305x.h>
+#include <rt305x_regs.h>
+#elif defined(CONFIG_RALINK_RT288X)
+#include <rt288x.h>
+#include <rt288x_regs.h>
+#else
+#error "Add support for your platform"
+#endif
+
+#include <asm/mach-ralink/ramips_spi.h>
+
+#define DRIVER_NAME "ramips-spi"
+#define RALINK_NUM_CHIPSELECTS 1 /* only one slave is supported*/
+#define RALINK_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
+#define SPICFG_CLK_PRESCALE_MASK 0x07
+
+//#define DEBUG
+
+#ifdef DEBUG
+#define spi_debug(args...) printk(args)
+#else
+#define spi_debug(args...)
+#endif
+
+
+struct ramips_spi {
+ struct work_struct work;
+
+ /* Lock access to transfer list. */
+ spinlock_t lock;
+
+ struct list_head msg_queue;
+ struct spi_master *master;
+ void __iomem *base;
+ unsigned int sys_freq;
+ unsigned int speed;
+};
+
+static struct workqueue_struct *ramips_spi_wq;
+
+static inline void __iomem *spi_reg(struct ramips_spi *ramips_spi, u32 reg)
+{
+ return ramips_spi->base + reg;
+}
+
+static inline void
+ramips_spi_setbits(struct ramips_spi *ramips_spi, u32 reg, u32 mask)
+{
+ void __iomem *reg_addr = spi_reg(ramips_spi, reg);
+ u32 val;
+
+ val = readl(reg_addr);
+ val |= mask;
+ writel(val, reg_addr);
+}
+
+static inline void
+ramips_spi_clrbits(struct ramips_spi *ramips_spi, u32 reg, u32 mask)
+{
+ void __iomem *reg_addr = spi_reg(ramips_spi, reg);
+ u32 val;
+
+ val = readl(reg_addr);
+ val &= ~mask;
+ writel(val, reg_addr);
+}
+
+static int ramips_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
+{
+
+ u32 rate;
+ u32 prescale;
+ u32 reg;
+ struct ramips_spi *ramips_spi = spi_master_get_devdata(spi->master);
+
+ spi_debug("%s: speed:%u\n", __func__, speed);
+
+ /*
+ * the supported rates are: 2,4,8...128
+ * round up as we look for equal or less speed
+ */
+ rate = DIV_ROUND_UP(ramips_spi->sys_freq, speed);
+ spi_debug("%s: rate-1:%u\n", __func__, rate);
+ rate = roundup_pow_of_two(rate);
+ spi_debug("%s: rate-2:%u\n", __func__, rate);
+
+ /* check if requested speed is too small */
+ if (rate > 128)
+ return -EINVAL;
+
+ if (rate < 2)
+ rate = 2;
+
+ /* Convert the rate to SPI clock divisor value. */
+ prescale = ilog2(rate/2);
+ spi_debug("%s: prescale:%u\n", __func__, prescale);
+
+ reg = readl(spi_reg(ramips_spi, RAMIPS_SPI_CFG));
+ reg = ((reg & ~SPICFG_CLK_PRESCALE_MASK) | prescale);
+ writel(reg, spi_reg(ramips_spi, RAMIPS_SPI_CFG));
+ ramips_spi->speed = speed;
+ return 0;
+}
+
+/*
+ * called only when no transfer is active on the bus
+ */
+static int
+ramips_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
+{
+ struct ramips_spi *ramips_spi = spi_master_get_devdata(spi->master);
+ unsigned int speed = spi->max_speed_hz;
+ int rc;
+ unsigned int bits_per_word = 8;
+
+ if ((t != NULL) && t->speed_hz)
+ speed = t->speed_hz;
+
+ if ((t != NULL) && t->bits_per_word)
+ bits_per_word = t->bits_per_word;
+
+ if(ramips_spi->speed != speed){
+ spi_debug("%s: speed_hz:%u\n", __func__, speed);
+ rc = ramips_spi_baudrate_set(spi, speed);
+ if (rc)
+ return rc;
+ }
+
+ if(bits_per_word != 8) {
+ spi_debug("%s: bad bits_per_word: %u\n", __func__, bits_per_word);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void ramips_spi_set_cs(struct ramips_spi *ramips_spi, int enable)
+{
+ if (enable)
+ ramips_spi_clrbits(ramips_spi, RAMIPS_SPI_CTL, SPICTL_SPIENA);
+ else
+ ramips_spi_setbits(ramips_spi, RAMIPS_SPI_CTL, SPICTL_SPIENA);
+}
+
+static inline int ramips_spi_wait_till_ready(struct ramips_spi *ramips_spi)
+{
+ int i;
+
+ for (i = 0; i < RALINK_SPI_WAIT_RDY_MAX_LOOP; i++) {
+ if (readl(spi_reg(ramips_spi, RAMIPS_SPI_STAT)) & SPISTAT_BUSY)
+ udelay(1);
+ else
+ return 1;
+ }
+
+ return -1;
+}
+
+static unsigned int
+ramips_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
+{
+ struct ramips_spi *ramips_spi = spi_master_get_devdata(spi->master);
+ unsigned count = 0;
+ u8 *rx = xfer->rx_buf;
+ const u8 *tx = xfer->tx_buf;
+ void __iomem *tx_rx_reg = spi_reg(ramips_spi, RAMIPS_SPI_DATA);
+
+ spi_debug("%s(%d): %s %s\n", __func__, xfer->len, (tx!=NULL)?("tx"):(" "), (rx!=NULL)?("rx"):(" "));
+ if(tx) {
+ for(count=0; count<xfer->len; count++){
+ writel(tx[count], tx_rx_reg);
+ ramips_spi_setbits(ramips_spi, RAMIPS_SPI_CTL, SPICTL_STARTWR);
+ if (ramips_spi_wait_till_ready(ramips_spi) < 0) {
+ dev_err(&spi->dev, "TXS timed out in %s\n", __func__);
+ goto out;
+ }
+ }
+ }
+
+ if(rx) {
+ for(count=0; count<xfer->len; count++){
+ ramips_spi_setbits(ramips_spi, RAMIPS_SPI_CTL, SPICTL_STARTRD);
+ if (ramips_spi_wait_till_ready(ramips_spi) < 0) {
+ dev_err(&spi->dev, "RXS timed out in %s\n", __func__);
+ goto out;
+ }
+ rx[count] = (u8 ) readl(tx_rx_reg);
+ }
+ }
+
+out:
+ return count;
+}
+
+
+static void ramips_spi_work(struct work_struct *work)
+{
+ struct ramips_spi *ramips_spi =
+ container_of(work, struct ramips_spi, work);
+
+ spin_lock_irq(&ramips_spi->lock);
+ while (!list_empty(&ramips_spi->msg_queue)) {
+ struct spi_message *m;
+ struct spi_device *spi;
+ struct spi_transfer *t = NULL;
+ int par_override = 0;
+ int status = 0;
+ int cs_active = 0;
+
+ m = container_of(ramips_spi->msg_queue.next, struct spi_message,
+ queue);
+
+ list_del_init(&m->queue);
+ spin_unlock_irq(&ramips_spi->lock);
+
+ spi = m->spi;
+
+ /* Load defaults */
+ status = ramips_spi_setup_transfer(spi, NULL);
+
+ if (status < 0)
+ goto msg_done;
+
+ list_for_each_entry(t, &m->transfers, transfer_list) {
+ if (par_override || t->speed_hz || t->bits_per_word) {
+ par_override = 1;
+ status = ramips_spi_setup_transfer(spi, t);
+ if (status < 0)
+ break;
+ if (!t->speed_hz && !t->bits_per_word)
+ par_override = 0;
+ }
+
+ if (!cs_active) {
+ ramips_spi_set_cs(ramips_spi, 1);
+ cs_active = 1;
+ }
+
+ if (t->len)
+ m->actual_length +=
+ ramips_spi_write_read(spi, t);
+
+ if (t->delay_usecs)
+ udelay(t->delay_usecs);
+
+ if (t->cs_change) {
+ ramips_spi_set_cs(ramips_spi, 0);
+ cs_active = 0;
+ }
+ }
+
+msg_done:
+ if (cs_active)
+ ramips_spi_set_cs(ramips_spi, 0);
+
+ m->status = status;
+ m->complete(m->context);
+
+ spin_lock_irq(&ramips_spi->lock);
+ }
+
+ spin_unlock_irq(&ramips_spi->lock);
+}
+
+static int __init ramips_spi_reset(struct ramips_spi *ramips_spi)
+{
+ u32 reg;
+ void __iomem *cfg_reg, *ctl_reg;
+
+ cfg_reg = spi_reg(ramips_spi, RAMIPS_SPI_CFG);
+ ctl_reg = spi_reg(ramips_spi, RAMIPS_SPI_CTL);
+
+ // GPIO-SPI mode
+ reg = rt305x_sysc_rr(SYSC_REG_GPIO_MODE);
+ reg &= ~(RT305X_GPIO_MODE_SPI);
+ rt305x_sysc_wr(reg, SYSC_REG_GPIO_MODE);
+
+ rt305x_sysc_wr(RT305X_RESET_SPI, SYSC_REG_RESET_CTRL);
+ udelay(1);
+
+ writel(SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL, cfg_reg);
+ writel(SPICTL_HIZSDO | SPICTL_SPIENA, ctl_reg);
+
+ return 0;
+}
+
+static int ramips_spi_setup(struct spi_device *spi)
+{
+ struct ramips_spi *ramips_spi = spi_master_get_devdata(spi->master);
+
+ if ((spi->max_speed_hz == 0)
+ || (spi->max_speed_hz > (ramips_spi->sys_freq/2)))
+ spi->max_speed_hz = (ramips_spi->sys_freq/2);
+
+ if (spi->max_speed_hz < (ramips_spi->sys_freq/128)) {
+ dev_err(&spi->dev, "setup: requested speed too low %d Hz\n",
+ spi->max_speed_hz);
+ return -EINVAL;
+ }
+
+ if(spi->bits_per_word != 0 && spi->bits_per_word != 8) {
+ dev_err(&spi->dev, "setup: requested bits per words - os wrong %d bpw\n",
+ spi->bits_per_word);
+ return -EINVAL;
+ }
+
+ if(spi->bits_per_word == 0)
+ spi->bits_per_word = 8;
+
+ /*
+ * baudrate & width will be set ramips_spi_setup_transfer
+ */
+ return 0;
+}
+
+static int ramips_spi_transfer(struct spi_device *spi, struct spi_message *m)
+{
+ struct ramips_spi *ramips_spi;
+ struct spi_transfer *t = NULL;
+ unsigned long flags;
+
+ m->actual_length = 0;
+ m->status = 0;
+
+ /* reject invalid messages and transfers */
+ if (list_empty(&m->transfers) || !m->complete)
+ return -EINVAL;
+
+ ramips_spi = spi_master_get_devdata(spi->master);
+
+ list_for_each_entry(t, &m->transfers, transfer_list) {
+ unsigned int bits_per_word = spi->bits_per_word;
+
+ if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
+ dev_err(&spi->dev,
+ "message rejected : "
+ "invalid transfer data buffers\n");
+ goto msg_rejected;
+ }
+
+ if (t->bits_per_word)
+ bits_per_word = t->bits_per_word;
+
+ if (bits_per_word != 8) {
+ dev_err(&spi->dev,
+ "message rejected : "
+ "invalid transfer bits_per_word (%d bits)\n",
+ bits_per_word);
+ goto msg_rejected;
+ }
+
+ if (t->speed_hz && t->speed_hz < (ramips_spi->sys_freq/128)) {
+ dev_err(&spi->dev,
+ "message rejected : "
+ "device min speed (%d Hz) exceeds "
+ "required transfer speed (%d Hz)\n",
+ (ramips_spi->sys_freq/128), t->speed_hz);
+ goto msg_rejected;
+ }
+ }
+
+
+ spin_lock_irqsave(&ramips_spi->lock, flags);
+ list_add_tail(&m->queue, &ramips_spi->msg_queue);
+ queue_work(ramips_spi_wq, &ramips_spi->work);
+ spin_unlock_irqrestore(&ramips_spi->lock, flags);
+
+ return 0;
+msg_rejected:
+ /* Message rejected and not queued */
+ m->status = -EINVAL;
+ if (m->complete)
+ m->complete(m->context);
+ return -EINVAL;
+}
+
+static int __init ramips_spi_probe(struct platform_device *pdev)
+{
+ struct spi_master *master;
+ struct ramips_spi *spi;
+ struct resource *r;
+ struct clk *clk;
+ int status = 0;
+
+ master = spi_alloc_master(&pdev->dev, sizeof *spi);
+ if (master == NULL) {
+ dev_dbg(&pdev->dev, "master allocation failed\n");
+ return -ENOMEM;
+ }
+
+ if (pdev->id != -1)
+ master->bus_num = pdev->id;
+
+ /* we support only mode 0, and no options */
+ master->mode_bits = 0;
+
+ master->setup = ramips_spi_setup;
+ master->transfer = ramips_spi_transfer;
+ master->num_chipselect = RALINK_NUM_CHIPSELECTS;
+
+ dev_set_drvdata(&pdev->dev, master);
+
+ spi = spi_master_get_devdata(master);
+ spi->master = master;
+
+
+ clk = clk_get(NULL, "sys");
+ if (IS_ERR(clk))
+ panic("unable to get SYS clock, err=%ld", PTR_ERR(clk));
+
+ spi->sys_freq = clk_get_rate(clk);
+ spi_debug("%s: sys_freq: %ld \n", __func__, spi->sys_freq);
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (r == NULL) {
+ status = -ENODEV;
+ goto out;
+ }
+
+ if (!request_mem_region(r->start, (r->end - r->start) + 1,
+ dev_name(&pdev->dev))) {
+ status = -EBUSY;
+ goto out;
+ }
+ spi->base = ioremap(r->start, resource_size(r));
+
+ INIT_WORK(&spi->work, ramips_spi_work);
+
+ spin_lock_init(&spi->lock);
+ INIT_LIST_HEAD(&spi->msg_queue);
+
+ if (ramips_spi_reset(spi) < 0)
+ goto out_rel_mem;
+
+ status = spi_register_master(master);
+ if (status < 0)
+ goto out_rel_mem;
+
+ return status;
+
+out_rel_mem:
+ release_mem_region(r->start, (r->end - r->start) + 1);
+
+out:
+ spi_master_put(master);
+ return status;
+}
+
+
+static int __exit ramips_spi_remove(struct platform_device *pdev)
+{
+ struct spi_master *master;
+ struct ramips_spi *spi;
+ struct resource *r;
+
+ master = dev_get_drvdata(&pdev->dev);
+ spi = spi_master_get_devdata(master);
+
+ cancel_work_sync(&spi->work);
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ release_mem_region(r->start, (r->end - r->start) + 1);
+
+ spi_unregister_master(master);
+
+ return 0;
+}
+
+MODULE_ALIAS("platform:" DRIVER_NAME);
+
+static struct platform_driver ramips_spi_driver = {
+ .driver = {
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
+ },
+ .remove = __exit_p(ramips_spi_remove),
+};
+
+static int __init ramips_spi_init(void)
+{
+ ramips_spi_wq = create_singlethread_workqueue(
+ ramips_spi_driver.driver.name);
+ if (ramips_spi_wq == NULL)
+ return -ENOMEM;
+
+ return platform_driver_probe(&ramips_spi_driver, ramips_spi_probe);
+}
+module_init(ramips_spi_init);
+
+static void __exit ramips_spi_exit(void)
+{
+ flush_workqueue(ramips_spi_wq);
+ platform_driver_unregister(&ramips_spi_driver);
+
+ destroy_workqueue(ramips_spi_wq);
+}
+module_exit(ramips_spi_exit);
+
+MODULE_DESCRIPTION("Ralink SPI driver");
+MODULE_AUTHOR("Sergiy <[email protected]>");
+MODULE_LICENSE("GPL");
Index: target/linux/ramips/patches-2.6.37/105-ramips-spi-driver.patch
===================================================================
--- target/linux/ramips/patches-2.6.37/105-ramips-spi-driver.patch (revision 0)
+++ target/linux/ramips/patches-2.6.37/105-ramips-spi-driver.patch (revision 0)
@@ -0,0 +1,25 @@
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -283,6 +283,12 @@ config SPI_PXA2XX
+ The driver can be configured to use any SSP port and additional
+ documentation can be found a Documentation/spi/pxa2xx.
+
++config SPI_RAMIPS
++ tristate "Ralink RT288x/RT305x SPI Controller"
++ depends on (SOC_RT288X || SOC_RT305X) && SPI_MASTER
++ help
++ This selects a driver for the Ralink RT288x/RT305x SPI Controller.
++
+ config SPI_S3C24XX
+ tristate "Samsung S3C24XX series SPI"
+ depends on ARCH_S3C2410 && EXPERIMENTAL
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -37,6 +37,7 @@ obj-$(CONFIG_SPI_FSL_LIB) += spi_fsl_li
+ obj-$(CONFIG_SPI_FSL_ESPI) += spi_fsl_espi.o
+ obj-$(CONFIG_SPI_FSL_SPI) += spi_fsl_spi.o
+ obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
++obj-$(CONFIG_SPI_RAMIPS) += ramips_spi.o
+ obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
+ obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx_hw.o
+ obj-$(CONFIG_SPI_S3C64XX) += spi_s3c64xx.o
Index: target/linux/ramips/rt305x/config-2.6.37
===================================================================
--- target/linux/ramips/rt305x/config-2.6.37 (revision 26927)
+++ target/linux/ramips/rt305x/config-2.6.37 (working copy)
@@ -106,6 +109,11 @@
# CONFIG_SLAB is not set
CONFIG_SLUB=y
CONFIG_SOC_RT305X=y
+CONFIG_SPI=y
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_RAMIPS=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
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