Hi all, This is a preliminary support for NB6 boards. The first patch add support for 6362 CPU. The chip is closed to the 6328 CPU, so the patch is mainly base on 6328 support.
The second patch add support for NB6 boards. NB6s provide different board IDs, but all use only one board layout. The boardid_fixup() is used to fix this point. Kind Regards, Miguel
>From a44847487d2582ffbd0e502568fdaf95fdf49dc1 Mon Sep 17 00:00:00 2001 From: Miguel GAIO <[email protected]> Date: Tue, 12 Jun 2012 15:48:45 +0200 Subject: [PATCH 1/2] * Add BCM6362 CPU support --- target/linux/brcm63xx/config-3.3 | 1 + ...IPS-BCM63XX-add-basic-BCM6362-CPU-support.patch | 540 ++++++++++++++++++++ .../401-MIPS-BCM63XX-register-ohci-device.patch | 9 +- .../403-MIPS-BCM63XX-register-ehci-device.patch | 6 +- .../408-6358-enet1-external-mii-clk.patch | 2 +- ...4-bcm63xx_enet-split-dma-registers-access.patch | 2 +- ...t-add-support-for-bcm6368-internal-ethern.patch | 2 +- ...X-add-HS-SPI-platform-device-and-register.patch | 2 +- .../419-SPI-MIPS-BCM63XX-Add-HS-SPI-driver.patch | 54 +- ...IPS-BCM63XX-Register-SPI-flash-if-present.patch | 16 +- .../427-MTD-m25p80-allow-passing-pp_data.patch | 16 +- ...0-MIPS-BCM63XX-pass-caldata-info-to-flash.patch | 2 +- .../brcm63xx/patches-3.3/511-board_V2500V.patch | 2 +- .../801-ssb_export_fallback_sprom.patch | 4 +- 14 files changed, 619 insertions(+), 39 deletions(-) create mode 100644 target/linux/brcm63xx/patches-3.3/350-MIPS-BCM63XX-add-basic-BCM6362-CPU-support.patch diff --git a/target/linux/brcm63xx/config-3.3 b/target/linux/brcm63xx/config-3.3 index 42ffabc..fed43ff 100644 --- a/target/linux/brcm63xx/config-3.3 +++ b/target/linux/brcm63xx/config-3.3 @@ -11,6 +11,7 @@ CONFIG_BCM63XX_CPU_6338=y CONFIG_BCM63XX_CPU_6345=y CONFIG_BCM63XX_CPU_6348=y CONFIG_BCM63XX_CPU_6358=y +CONFIG_BCM63XX_CPU_6362=y CONFIG_BCM63XX_CPU_6368=y CONFIG_BCM63XX_ENET=y CONFIG_BCM63XX_PHY=y diff --git a/target/linux/brcm63xx/patches-3.3/350-MIPS-BCM63XX-add-basic-BCM6362-CPU-support.patch b/target/linux/brcm63xx/patches-3.3/350-MIPS-BCM63XX-add-basic-BCM6362-CPU-support.patch new file mode 100644 index 0000000..10f99a8 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.3/350-MIPS-BCM63XX-add-basic-BCM6362-CPU-support.patch @@ -0,0 +1,540 @@ +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -25,6 +25,10 @@ config BCM63XX_CPU_6358 + bool "support 6358 CPU" + select HW_HAS_PCI + ++config BCM63XX_CPU_6362 ++ bool "support 6362 CPU" ++ select HW_HAS_PCI ++ + config BCM63XX_CPU_6368 + bool "support 6368 CPU" + select HW_HAS_PCI +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -762,8 +762,8 @@ void __init board_prom_init(void) + u32 val; + + /* read base address of boot chip select (0) +- * 6328 does not have MPI but boots from a fixed address */ +- if (BCMCPU_IS_6328()) ++ * 6328,6362 does not have MPI but boots from a fixed address */ ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) + val = 0x18000000; + else { + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -71,6 +71,15 @@ static const int bcm6358_irqs[] = { + + }; + ++static const unsigned long bcm6362_regs_base[] = { ++ __GEN_CPU_REGS_TABLE(6362) ++}; ++ ++static const int bcm6362_irqs[] = { ++ __GEN_CPU_IRQ_TABLE(6362) ++ ++}; ++ + static const unsigned long bcm6368_regs_base[] = { + __GEN_CPU_REGS_TABLE(6368) + }; +@@ -169,6 +178,44 @@ static unsigned int detect_cpu_clock(voi + return (16 * 1000000 * n1 * n2) / m1; + } + ++ case BCM6362_CPU_ID: ++ { ++ unsigned int tmp, mips_pll_fcvo; ++ ++ tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG); ++ mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK) ++ >> STRAPBUS_6362_FCVO_SHIFT; ++ ++ switch (mips_pll_fcvo) { ++ case 0x04: ++ case 0x0c: ++ case 0x14: ++ case 0x1c: ++ return 160000000; ++ case 0x15: ++ case 0x1d: ++ return 200000000; ++ case 0x03: ++ case 0x0b: ++ case 0x13: ++ case 0x1b: ++ return 240000000; ++ case 0x07: ++ case 0x17: ++ return 384000000; ++ case 0x05: ++ case 0x06: ++ case 0x0e: ++ case 0x16: ++ case 0x1e: ++ case 0x1f: ++ return 400000000; ++ default: ++ return 320000000; ++ } ++ ++ } ++ + case BCM6368_CPU_ID: + { + unsigned int tmp, p1, p2, ndiv, m1; +@@ -205,7 +252,7 @@ static unsigned int detect_memory_size(v + unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; + u32 val; + +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) + return bcm_ddr_readl(DDR_CSEND_REG) << 24; + + if (BCMCPU_IS_6345()) { +@@ -280,6 +327,11 @@ void __init bcm63xx_cpu_init(void) + bcm63xx_regs_base = bcm6328_regs_base; + bcm63xx_irqs = bcm6328_irqs; + break; ++ case BCM6362_CPU_ID: ++ expected_cpu_id = BCM6362_CPU_ID; ++ bcm63xx_regs_base = bcm6362_regs_base; ++ bcm63xx_irqs = bcm6362_irqs; ++ break; + case BCM6368_CPU_ID: + expected_cpu_id = BCM6368_CPU_ID; + bcm63xx_regs_base = bcm6368_regs_base; +--- a/arch/mips/bcm63xx/dev-spi.c ++++ b/arch/mips/bcm63xx/dev-spi.c +@@ -47,7 +47,7 @@ static __init void bcm63xx_spi_regs_init + bcm63xx_regs_spi = bcm6338_regs_spi; + if (BCMCPU_IS_6348()) + bcm63xx_regs_spi = bcm6348_regs_spi; +- if (BCMCPU_IS_6358()) ++ if (BCMCPU_IS_6358() || BCMCPU_IS_6362()) + bcm63xx_regs_spi = bcm6358_regs_spi; + if (BCMCPU_IS_6368()) + bcm63xx_regs_spi = bcm6368_regs_spi; +@@ -108,7 +108,7 @@ int __init bcm63xx_spi_register(void) + spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE; + } + +- if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) { ++ if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) { + spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; + spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE; + } +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -82,6 +82,17 @@ static void __internal_irq_unmask_64(uns + #define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358 + #define ext_irq_cfg_reg2 0 + #endif ++#ifdef CONFIG_BCM63XX_CPU_6362 ++#define irq_stat_reg PERF_IRQSTAT_6362_REG ++#define irq_mask_reg PERF_IRQMASK_6362_REG ++#define irq_bits 64 ++#define is_ext_irq_cascaded 1 ++#define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE) ++#define ext_irq_end (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE) ++#define ext_irq_count 4 ++#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6362 ++#define ext_irq_cfg_reg2 PERF_EXTIRQ_CFG_REG2_6362 ++#endif + #ifdef CONFIG_BCM63XX_CPU_6368 + #define irq_stat_reg PERF_IRQSTAT_6368_REG + #define irq_mask_reg PERF_IRQMASK_6368_REG +@@ -170,6 +181,17 @@ static void bcm63xx_init_irq(void) + ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; + break; ++ case BCM6362_CPU_ID: ++ irq_stat_addr += PERF_IRQSTAT_6362_REG; ++ irq_mask_addr += PERF_IRQMASK_6362_REG; ++ irq_bits = 64; ++ ext_irq_count = 4; ++ is_ext_irq_cascaded = 1; ++ ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE; ++ ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE; ++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362; ++ ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6362; ++ break; + case BCM6368_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6368_REG; + irq_mask_addr += PERF_IRQMASK_6368_REG; +@@ -457,6 +479,7 @@ static int bcm63xx_external_irq_set_type + case BCM6338_CPU_ID: + case BCM6345_CPU_ID: + case BCM6358_CPU_ID: ++ case BCM6362_CPU_ID: + case BCM6368_CPU_ID: + if (levelsense) + reg |= EXTIRQ_CFG_LEVELSENSE(irq); +--- a/arch/mips/bcm63xx/prom.c ++++ b/arch/mips/bcm63xx/prom.c +@@ -36,6 +36,8 @@ void __init prom_init(void) + mask = CKCTL_6348_ALL_SAFE_EN; + else if (BCMCPU_IS_6358()) + mask = CKCTL_6358_ALL_SAFE_EN; ++ else if (BCMCPU_IS_6362()) ++ mask = CKCTL_6362_ALL_SAFE_EN; + else if (BCMCPU_IS_6368()) + mask = CKCTL_6368_ALL_SAFE_EN; + else +--- a/arch/mips/bcm63xx/setup.c ++++ b/arch/mips/bcm63xx/setup.c +@@ -83,6 +83,9 @@ void bcm63xx_machine_reboot(void) + case BCM6358_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358; + break; ++ case BCM6362_CPU_ID: ++ perf_regs[0] = PERF_EXTIRQ_CFG_REG_6362; ++ break; + } + + for (i = 0; i < 2; i++) { +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -14,6 +14,7 @@ + #define BCM6345_CPU_ID 0x6345 + #define BCM6348_CPU_ID 0x6348 + #define BCM6358_CPU_ID 0x6358 ++#define BCM6362_CPU_ID 0x6362 + #define BCM6368_CPU_ID 0x6368 + + void __init bcm63xx_cpu_init(void); +@@ -86,6 +87,19 @@ unsigned int bcm63xx_get_cpu_freq(void); + # define BCMCPU_IS_6358() (0) + #endif + ++#ifdef CONFIG_BCM63XX_CPU_6362 ++# ifdef bcm63xx_get_cpu_id ++# undef bcm63xx_get_cpu_id ++# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() ++# define BCMCPU_RUNTIME_DETECT ++# else ++# define bcm63xx_get_cpu_id() BCM6362_CPU_ID ++# endif ++# define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) ++#else ++# define BCMCPU_IS_6362() (0) ++#endif ++ + #ifdef CONFIG_BCM63XX_CPU_6368 + # ifdef bcm63xx_get_cpu_id + # undef bcm63xx_get_cpu_id +@@ -393,6 +407,48 @@ enum bcm63xx_regs_set { + #define BCM_6358_TRNG_BASE (0xdeadbeef) + #define BCM_6358_MISC_BASE (0xdeadbeef) + ++/* ++ * 6362 register sets base address ++ */ ++#define BCM_6362_DSL_LMEM_BASE (0xdeadbeef) ++#define BCM_6362_PERF_BASE (0xb0000000) ++#define BCM_6362_TIMER_BASE (0xb0000040) ++#define BCM_6362_WDT_BASE (0xb000005c) ++#define BCM_6362_UART0_BASE (0xb0000100) ++#define BCM_6362_UART1_BASE (0xb0000120) ++#define BCM_6362_GPIO_BASE (0xb0000080) ++#define BCM_6362_SPI_BASE (0xb0000800) ++#define BCM_6362_UDC0_BASE (0xdeadbeef) ++#define BCM_6362_OHCI0_BASE (0xb0002600) ++#define BCM_6362_OHCI_PRIV_BASE (0xdeadbeef) ++#define BCM_6362_USBH_PRIV_BASE (0xb0002700) ++#define BCM_6362_MPI_BASE (0xdeadbeef) ++#define BCM_6362_PCMCIA_BASE (0xdeadbeef) ++#define BCM_6362_PCIE_BASE (0xbe040000) ++#define BCM_6362_DSL_BASE (0xdeadbeef) ++#define BCM_6362_ENET0_BASE (0xdeadbeef) ++#define BCM_6362_ENET1_BASE (0xdeadbeef) ++#define BCM_6362_ENETDMA_BASE (0xdeadbeef) ++#define BCM_6362_ENETDMAC_BASE (0xdeadbeef) ++#define BCM_6362_ENETDMAS_BASE (0xdeadbeef) ++#define BCM_6362_ENETSW_BASE (0xdeadbeef) ++#define BCM_6362_EHCI0_BASE (0xb0002500) ++#define BCM_6362_SDRAM_BASE (0xdeadbeef) ++#define BCM_6362_MEMC_BASE (0xdeadbeef) ++#define BCM_6362_DDR_BASE (0xb0003000) ++#define BCM_6362_M2M_BASE (0xdeadbeef) ++#define BCM_6362_ATM_BASE (0xdeadbeef) ++#define BCM_6362_XTM_BASE (0xdeadbeef) ++#define BCM_6362_XTMDMA_BASE (0xdeadbeef) ++#define BCM_6362_XTMDMAC_BASE (0xdeadbeef) ++#define BCM_6362_XTMDMAS_BASE (0xdeadbeef) ++#define BCM_6362_PCM_BASE (0xb000a000) ++#define BCM_6362_PCMDMA_BASE (0xb000a800) ++#define BCM_6362_PCMDMAC_BASE (0xb000aa00) ++#define BCM_6362_PCMDMAS_BASE (0xb000ac00) ++#define BCM_6362_TRNG_BASE (0xdeadbeef) ++#define BCM_6362_MISC_BASE (0xb0001800) ++ + + /* + * 6368 register sets base address +@@ -547,6 +603,9 @@ static inline unsigned long bcm63xx_regs + #ifdef CONFIG_BCM63XX_CPU_6358 + __GEN_RSET(6358) + #endif ++#ifdef CONFIG_BCM63XX_CPU_6362 ++ __GEN_RSET(6362) ++#endif + #ifdef CONFIG_BCM63XX_CPU_6368 + __GEN_RSET(6368) + #endif +@@ -761,6 +820,45 @@ enum bcm63xx_irq { + #define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) + + /* ++ * 6362 irqs ++ */ ++#define BCM_6362_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) ++#define BCM_6362_SPI_IRQ (IRQ_INTERNAL_BASE + 2) ++#define BCM_6362_UART0_IRQ (IRQ_INTERNAL_BASE + 3) ++#define BCM_6362_UART1_IRQ (IRQ_INTERNAL_BASE + 4) ++#define BCM_6362_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8) ++#define BCM_6362_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) ++#define BCM_6362_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) ++#define BCM_6362_DSL_IRQ 0 ++#define BCM_6362_ENET0_IRQ 0 ++#define BCM_6362_ENET1_IRQ 0 ++#define BCM_6362_ENET_PHY_IRQ 0 ++#define BCM_6362_ENET0_RXDMA_IRQ 0 ++#define BCM_6362_ENET0_TXDMA_IRQ 0 ++#define BCM_6362_ENET1_RXDMA_IRQ 0 ++#define BCM_6362_ENET1_TXDMA_IRQ 0 ++#define BCM_6362_PCI_IRQ 0 ++#define BCM_6362_PCMCIA_IRQ 0 ++#define BCM_6362_ATM_IRQ 0 ++#define BCM_6362_ENETSW_RXDMA0_IRQ 0 ++#define BCM_6362_ENETSW_RXDMA1_IRQ 0 ++#define BCM_6362_ENETSW_RXDMA2_IRQ 0 ++#define BCM_6362_ENETSW_RXDMA3_IRQ 0 ++#define BCM_6362_ENETSW_TXDMA0_IRQ 0 ++#define BCM_6362_ENETSW_TXDMA1_IRQ 0 ++#define BCM_6362_ENETSW_TXDMA2_IRQ 0 ++#define BCM_6362_ENETSW_TXDMA3_IRQ 0 ++#define BCM_6362_XTM_IRQ 0 ++#define BCM_6362_XTM_DMA0_IRQ 0 ++ ++#define BCM_6362_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 36) ++#define BCM_6362_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 37) ++#define BCM_6362_EXT_IRQ0 (IRQ_INTERNAL_BASE + 40) ++#define BCM_6362_EXT_IRQ1 (IRQ_INTERNAL_BASE + 41) ++#define BCM_6362_EXT_IRQ2 (IRQ_INTERNAL_BASE + 42) ++#define BCM_6362_EXT_IRQ3 (IRQ_INTERNAL_BASE + 43) ++ ++/* + * 6368 irqs + */ + #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +@@ -10,6 +10,7 @@ static inline unsigned long bcm63xx_gpio + { + switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: ++ case BCM6362_CPU_ID: + return 32; + case BCM6358_CPU_ID: + return 40; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -107,6 +107,39 @@ + CKCTL_6358_USBSU_EN | \ + CKCTL_6358_EPHY_EN) + ++#define CKCTL_6362_DISABLE_GLESS (1 << 0) ++#define CKCTL_6362_ADSL_QPROC_EN (1 << 1) ++#define CKCTL_6362_ADSL_AFE_EN (1 << 2) ++#define CKCTL_6362_ADSL_EN (1 << 3) ++#define CKCTL_6362_MIPS_EN (1 << 4) ++#define CKCTL_6362_WLAN_OCP_EN (1 << 5) ++#define CKCTL_6362_SWPKT_USB_EN (1 << 7) ++#define CKCTL_6362_SWPKT_SAR_EN (1 << 8) ++#define CKCTL_6362_SAR_EN (1 << 9) ++#define CKCTL_6362_ROBOSW_EN (1 << 10) ++#define CKCTL_6362_PCM_EN (1 << 11) ++#define CKCTL_6362_USBD_EN (1 << 12) ++#define CKCTL_6362_USBH_EN (1 << 13) ++#define CKCTL_6362_IPSEC_EN (1 << 14) ++#define CKCTL_6362_SPI_EN (1 << 15) ++#define CKCTL_6362_HS_SPI_EN (1 << 16) ++#define CKCTL_6362_PCIE_EN (1 << 17) ++#define CKCTL_6362_FAP_EN (1 << 18) ++#define CKCTL_6362_PHYMIPS_EN (1 << 19) ++#define CKCTL_6362_NAND_EN (1 << 20) ++ ++#define CKCTL_6362_ALL_SAFE_EN (CKCTL_6362_ADSL_QPROC_EN | \ ++ CKCTL_6362_ADSL_AFE_EN | \ ++ CKCTL_6362_ADSL_EN | \ ++ CKCTL_6362_WLAN_OCP_EN | \ ++ CKCTL_6362_USBD_EN | \ ++ CKCTL_6362_USBH_EN | \ ++ CKCTL_6362_IPSEC_EN | \ ++ CKCTL_6362_HS_SPI_EN | \ ++ CKCTL_6362_PCIE_EN | \ ++ CKCTL_6362_FAP_EN | \ ++ CKCTL_6362_NAND_EN) ++ + #define CKCTL_6368_VDSL_QPROC_EN (1 << 2) + #define CKCTL_6368_VDSL_AFE_EN (1 << 3) + #define CKCTL_6368_VDSL_BONDING_EN (1 << 4) +@@ -148,6 +181,7 @@ + #define PERF_IRQMASK_6345_REG 0xc + #define PERF_IRQMASK_6348_REG 0xc + #define PERF_IRQMASK_6358_REG 0xc ++#define PERF_IRQMASK_6362_REG 0x20 + #define PERF_IRQMASK_6368_REG 0x20 + + /* Interrupt Status register */ +@@ -156,6 +190,7 @@ + #define PERF_IRQSTAT_6345_REG 0x10 + #define PERF_IRQSTAT_6348_REG 0x10 + #define PERF_IRQSTAT_6358_REG 0x10 ++#define PERF_IRQSTAT_6362_REG 0x28 + #define PERF_IRQSTAT_6368_REG 0x28 + + /* External Interrupt Configuration register */ +@@ -164,8 +199,10 @@ + #define PERF_EXTIRQ_CFG_REG_6345 0x14 + #define PERF_EXTIRQ_CFG_REG_6348 0x14 + #define PERF_EXTIRQ_CFG_REG_6358 0x14 ++#define PERF_EXTIRQ_CFG_REG_6362 0x18 + #define PERF_EXTIRQ_CFG_REG_6368 0x18 + ++#define PERF_EXTIRQ_CFG_REG2_6362 0x1c + #define PERF_EXTIRQ_CFG_REG2_6368 0x1c + + /* for 6348 only */ +@@ -191,6 +228,7 @@ + /* Soft Reset register */ + #define PERF_SOFTRESET_REG 0x28 + #define PERF_SOFTRESET_6328_REG 0x10 ++#define PERF_SOFTRESET_6362_REG 0x10 + #define PERF_SOFTRESET_6368_REG 0x10 + + #define SOFTRESET_6328_SPI_MASK (1 << 0) +@@ -244,6 +282,38 @@ + SOFTRESET_6348_ACLC_MASK | \ + SOFTRESET_6348_ADSLMIPSPLL_MASK) + ++#define SOFTRESET_6362_WLAN_SHIM_UBUS_MASK (1 << 14) ++#define SOFTRESET_6362_FAP_MASK (1 << 13) ++#define SOFTRESET_6362_DDR_PHY_MASK (1 << 12) ++#define SOFTRESET_6362_WLAN_SHIM_MASK (1 << 11) ++#define SOFTRESET_6362_PCIE_EXT_MASK (1 << 10) ++#define SOFTRESET_6362_PCIE_MASK (1 << 9) ++#define SOFTRESET_6362_PCIE_CORE_MASK (1 << 8) ++#define SOFTRESET_6362_PCM_MASK (1 << 7) ++#define SOFTRESET_6362_USBH_MASK (1 << 6) ++#define SOFTRESET_6362_USBD_MASK (1 << 5) ++#define SOFTRESET_6362_SWITCH_MASK (1 << 4) ++#define SOFTRESET_6362_SAR_MASK (1 << 3) ++#define SOFTRESET_6362_EPHY_MASK (1 << 2) ++#define SOFTRESET_6362_IPSEC_MASK (1 << 1) ++#define SOFTRESET_6362_SPI_MASK (1 << 0) ++ ++#define SOFTRESET_6362_ALL (SOFTRESET_6362_WLAN_SHIM_UBUS_MASK | \ ++ SOFTRESET_6362_FAP_MASK | \ ++ SOFTRESET_6362_DDR_PHY_MASK | \ ++ SOFTRESET_6362_WLAN_SHIM_MASK | \ ++ SOFTRESET_6362_PCIE_EXT_MASK | \ ++ SOFTRESET_6362_PCIE_MASK | \ ++ SOFTRESET_6362_PCIE_CORE_MASK | \ ++ SOFTRESET_6362_PCM_MASK | \ ++ SOFTRESET_6362_USBH_MASK | \ ++ SOFTRESET_6362_USBD_MASK | \ ++ SOFTRESET_6362_SWITCH_MASK | \ ++ SOFTRESET_6362_SAR_MASK | \ ++ SOFTRESET_6362_EPHY_MASK | \ ++ SOFTRESET_6362_IPSEC_MASK | \ ++ SOFTRESET_6362_SPI_MASK) ++ + #define SOFTRESET_6368_SPI_MASK (1 << 0) + #define SOFTRESET_6368_MPI_MASK (1 << 3) + #define SOFTRESET_6368_EPHY_MASK (1 << 6) +@@ -769,6 +839,7 @@ + *************************************************************************/ + + #define USBH_PRIV_SWAP_6358_REG 0x0 ++#define USBH_PRIV_SWAP_6362_REG 0x1c + #define USBH_PRIV_SWAP_6368_REG 0x1c + + #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 +@@ -781,8 +852,10 @@ + #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) + + #define USBH_PRIV_TEST_6358_REG 0x24 ++#define USBH_PRIV_TEST_6362_REG 0x14 + #define USBH_PRIV_TEST_6368_REG 0x14 + ++#define USBH_PRIV_SETUP_6362_REG 0x28 + #define USBH_PRIV_SETUP_6368_REG 0x28 + #define USBH_PRIV_SETUP_IOC_SHIFT 4 + #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) +@@ -1173,6 +1246,13 @@ + #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28) + #define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28) + ++ ++#define MISC_STRAPBUS_6362_REG 0x14 ++#define STRAPBUS_6362_FCVO_SHIFT 1 ++#define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT) ++#define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15) ++#define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15) ++ + /************************************************************************* + * _REG relative to RSET_PCIE + *************************************************************************/ +--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h ++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h +@@ -19,6 +19,7 @@ static inline int is_bcm63xx_internal_re + return 1; + break; + case BCM6328_CPU_ID: ++ case BCM6362_CPU_ID: + case BCM6368_CPU_ID: + if (offset >= 0xb0000000 && offset < 0xb1000000) + return 1; +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -76,6 +76,12 @@ static int __init bcm63xx_detect_flash_t + return BCM63XX_FLASH_TYPE_PARALLEL; + else + return BCM63XX_FLASH_TYPE_SERIAL; ++ case BCM6362_CPU_ID: ++ val = bcm_misc_readl(MISC_STRAPBUS_6362_REG); ++ if (val & STRAPBUS_6362_BOOT_SEL_SERIAL) ++ return BCM63XX_FLASH_TYPE_SERIAL; ++ else ++ return BCM63XX_FLASH_TYPE_NAND; + case BCM6368_CPU_ID: + val = bcm_gpio_readl(GPIO_STRAPBUS_REG); + switch (val & STRAPBUS_6368_BOOT_SEL_MASK) { +--- a/arch/mips/bcm63xx/dev-uart.c ++++ b/arch/mips/bcm63xx/dev-uart.c +@@ -55,7 +55,7 @@ int __init bcm63xx_uart_register(unsigne + return -ENODEV; + + if (id == 1 && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() && +- !BCMCPU_IS_6368()) ++ !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) + return -ENODEV; + + if (id == 0) { +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -202,6 +202,8 @@ static void hsspi_set(struct clk *clk, i + + if (BCMCPU_IS_6328()) + mask = CKCTL_6328_HSSPI_EN; ++ else if (BCMCPU_IS_6362()) ++ mask = CKCTL_6362_HS_SPI_EN; + else + return; + diff --git a/target/linux/brcm63xx/patches-3.3/401-MIPS-BCM63XX-register-ohci-device.patch b/target/linux/brcm63xx/patches-3.3/401-MIPS-BCM63XX-register-ohci-device.patch index fc70409..85ce977 100644 --- a/target/linux/brcm63xx/patches-3.3/401-MIPS-BCM63XX-register-ohci-device.patch +++ b/target/linux/brcm63xx/patches-3.3/401-MIPS-BCM63XX-register-ohci-device.patch @@ -15,7 +15,7 @@ Subject: [PATCH 24/63] MIPS: BCM63XX: register ohci device. --- a/arch/mips/bcm63xx/Kconfig +++ b/arch/mips/bcm63xx/Kconfig -@@ -8,26 +8,25 @@ config BCM63XX_CPU_6328 +@@ -8,30 +8,30 @@ config BCM63XX_CPU_6328 config BCM63XX_CPU_6338 bool "support 6338 CPU" select HW_HAS_PCI @@ -39,6 +39,11 @@ Subject: [PATCH 24/63] MIPS: BCM63XX: register ohci device. select HW_HAS_PCI + select USB_ARCH_HAS_OHCI if USB_SUPPORT + config BCM63XX_CPU_6362 + bool "support 6362 CPU" + select HW_HAS_PCI ++ select USB_ARCH_HAS_OHCI if USB_SUPPORT + config BCM63XX_CPU_6368 bool "support 6368 CPU" select HW_HAS_PCI @@ -120,7 +125,7 @@ Subject: [PATCH 24/63] MIPS: BCM63XX: register ohci device. + +int __init bcm63xx_ohci_register(void) +{ -+ if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368()) ++ if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) + return 0; + + ohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0); diff --git a/target/linux/brcm63xx/patches-3.3/403-MIPS-BCM63XX-register-ehci-device.patch b/target/linux/brcm63xx/patches-3.3/403-MIPS-BCM63XX-register-ehci-device.patch index f182961..528dbfe 100644 --- a/target/linux/brcm63xx/patches-3.3/403-MIPS-BCM63XX-register-ehci-device.patch +++ b/target/linux/brcm63xx/patches-3.3/403-MIPS-BCM63XX-register-ehci-device.patch @@ -15,8 +15,8 @@ Subject: [PATCH 26/63] MIPS: BCM63XX: register ehci device. --- a/arch/mips/bcm63xx/Kconfig +++ b/arch/mips/bcm63xx/Kconfig -@@ -22,11 +22,13 @@ config BCM63XX_CPU_6358 - bool "support 6358 CPU" +@@ -27,11 +27,13 @@ config BCM63XX_CPU_6362 + bool "support 6362 CPU" select HW_HAS_PCI select USB_ARCH_HAS_OHCI if USB_SUPPORT + select USB_ARCH_HAS_EHCI if USB_SUPPORT @@ -103,7 +103,7 @@ Subject: [PATCH 26/63] MIPS: BCM63XX: register ehci device. + +int __init bcm63xx_ehci_register(void) +{ -+ if (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()) ++ if (!BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) + return 0; + + ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); diff --git a/target/linux/brcm63xx/patches-3.3/408-6358-enet1-external-mii-clk.patch b/target/linux/brcm63xx/patches-3.3/408-6358-enet1-external-mii-clk.patch index e504552..fd36434 100644 --- a/target/linux/brcm63xx/patches-3.3/408-6358-enet1-external-mii-clk.patch +++ b/target/linux/brcm63xx/patches-3.3/408-6358-enet1-external-mii-clk.patch @@ -11,7 +11,7 @@ bcm_gpio_writel(val, GPIO_MODE_REG); --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h -@@ -510,6 +510,8 @@ +@@ -580,6 +580,8 @@ #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7) #define GPIO_MODE_6358_SERIAL_LED (1 << 10) #define GPIO_MODE_6358_UTOPIA (1 << 12) diff --git a/target/linux/brcm63xx/patches-3.3/414-bcm63xx_enet-split-dma-registers-access.patch b/target/linux/brcm63xx/patches-3.3/414-bcm63xx_enet-split-dma-registers-access.patch index 512f53f..1661f3c 100644 --- a/target/linux/brcm63xx/patches-3.3/414-bcm63xx_enet-split-dma-registers-access.patch +++ b/target/linux/brcm63xx/patches-3.3/414-bcm63xx_enet-split-dma-registers-access.patch @@ -50,7 +50,7 @@ Subject: [PATCH 30/63] bcm63xx_enet: split dma registers access. if (ret) --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h -@@ -156,7 +156,9 @@ enum bcm63xx_regs_set { +@@ -170,7 +170,9 @@ enum bcm63xx_regs_set { #define BCM_6358_RSET_SPI_SIZE 1804 #define BCM_6368_RSET_SPI_SIZE 1804 #define RSET_ENET_SIZE 2048 diff --git a/target/linux/brcm63xx/patches-3.3/415-bcm63xx_enet-add-support-for-bcm6368-internal-ethern.patch b/target/linux/brcm63xx/patches-3.3/415-bcm63xx_enet-add-support-for-bcm6368-internal-ethern.patch index d6dbaa0..e4eac08 100644 --- a/target/linux/brcm63xx/patches-3.3/415-bcm63xx_enet-add-support-for-bcm6368-internal-ethern.patch +++ b/target/linux/brcm63xx/patches-3.3/415-bcm63xx_enet-add-support-for-bcm6368-internal-ethern.patch @@ -205,7 +205,7 @@ Subject: [PATCH 31/63] bcm63xx_enet: add support for bcm6368 internal ethernet s #endif /* ! BCM63XX_DEV_ENET_H_ */ --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h -@@ -750,10 +750,60 @@ +@@ -820,10 +820,60 @@ * _REG relative to RSET_ENETSW *************************************************************************/ diff --git a/target/linux/brcm63xx/patches-3.3/418-MIPS-BCM63XX-add-HS-SPI-platform-device-and-register.patch b/target/linux/brcm63xx/patches-3.3/418-MIPS-BCM63XX-add-HS-SPI-platform-device-and-register.patch index a1f43be..06acb8c 100644 --- a/target/linux/brcm63xx/patches-3.3/418-MIPS-BCM63XX-add-HS-SPI-platform-device-and-register.patch +++ b/target/linux/brcm63xx/patches-3.3/418-MIPS-BCM63XX-add-HS-SPI-platform-device-and-register.patch @@ -93,7 +93,7 @@ Signed-off-by: Jonas Gorski <[email protected]> +int __init bcm63xx_hsspi_register(void) +{ + -+ if (!BCMCPU_IS_6328()) ++ if (!(BCMCPU_IS_6328() || BCMCPU_IS_6362())) + return -ENODEV; + + spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI); diff --git a/target/linux/brcm63xx/patches-3.3/419-SPI-MIPS-BCM63XX-Add-HS-SPI-driver.patch b/target/linux/brcm63xx/patches-3.3/419-SPI-MIPS-BCM63XX-Add-HS-SPI-driver.patch index 94c9eee..bbcc0c5 100644 --- a/target/linux/brcm63xx/patches-3.3/419-SPI-MIPS-BCM63XX-Add-HS-SPI-driver.patch +++ b/target/linux/brcm63xx/patches-3.3/419-SPI-MIPS-BCM63XX-Add-HS-SPI-driver.patch @@ -18,7 +18,7 @@ Signed-off-by: Jonas Gorski <[email protected]> --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h -@@ -116,6 +116,7 @@ enum bcm63xx_regs_set { +@@ -130,6 +130,7 @@ enum bcm63xx_regs_set { RSET_UART1, RSET_GPIO, RSET_SPI, @@ -26,7 +26,7 @@ Signed-off-by: Jonas Gorski <[email protected]> RSET_UDC0, RSET_OHCI0, RSET_OHCI_PRIV, -@@ -161,6 +162,7 @@ enum bcm63xx_regs_set { +@@ -175,6 +176,7 @@ enum bcm63xx_regs_set { #define RSET_ENETDMAS_SIZE(chans) (16 * (chans)) #define RSET_ENETSW_SIZE 65536 #define RSET_UART_SIZE 24 @@ -34,7 +34,7 @@ Signed-off-by: Jonas Gorski <[email protected]> #define RSET_UDC_SIZE 256 #define RSET_OHCI_SIZE 256 #define RSET_EHCI_SIZE 256 -@@ -184,6 +186,7 @@ enum bcm63xx_regs_set { +@@ -198,6 +200,7 @@ enum bcm63xx_regs_set { #define BCM_6328_UART1_BASE (0xb0000120) #define BCM_6328_GPIO_BASE (0xb0000080) #define BCM_6328_SPI_BASE (0xdeadbeef) @@ -42,7 +42,7 @@ Signed-off-by: Jonas Gorski <[email protected]> #define BCM_6328_UDC0_BASE (0xdeadbeef) #define BCM_6328_USBDMA_BASE (0xdeadbeef) #define BCM_6328_OHCI0_BASE (0xdeadbeef) -@@ -229,6 +232,7 @@ enum bcm63xx_regs_set { +@@ -243,6 +246,7 @@ enum bcm63xx_regs_set { #define BCM_6338_UART1_BASE (0xdeadbeef) #define BCM_6338_GPIO_BASE (0xfffe0400) #define BCM_6338_SPI_BASE (0xfffe0c00) @@ -50,7 +50,7 @@ Signed-off-by: Jonas Gorski <[email protected]> #define BCM_6338_UDC0_BASE (0xdeadbeef) #define BCM_6338_USBDMA_BASE (0xfffe2400) #define BCM_6338_OHCI0_BASE (0xdeadbeef) -@@ -275,6 +279,7 @@ enum bcm63xx_regs_set { +@@ -289,6 +293,7 @@ enum bcm63xx_regs_set { #define BCM_6345_UART1_BASE (0xdeadbeef) #define BCM_6345_GPIO_BASE (0xfffe0400) #define BCM_6345_SPI_BASE (0xdeadbeef) @@ -58,7 +58,7 @@ Signed-off-by: Jonas Gorski <[email protected]> #define BCM_6345_UDC0_BASE (0xdeadbeef) #define BCM_6345_USBDMA_BASE (0xfffe2800) #define BCM_6345_ENET0_BASE (0xfffe1800) -@@ -320,6 +325,7 @@ enum bcm63xx_regs_set { +@@ -334,6 +339,7 @@ enum bcm63xx_regs_set { #define BCM_6348_UART1_BASE (0xdeadbeef) #define BCM_6348_GPIO_BASE (0xfffe0400) #define BCM_6348_SPI_BASE (0xfffe0c00) @@ -66,7 +66,7 @@ Signed-off-by: Jonas Gorski <[email protected]> #define BCM_6348_UDC0_BASE (0xfffe1000) #define BCM_6348_OHCI0_BASE (0xfffe1b00) #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) -@@ -363,6 +369,7 @@ enum bcm63xx_regs_set { +@@ -377,6 +383,7 @@ enum bcm63xx_regs_set { #define BCM_6358_UART1_BASE (0xfffe0120) #define BCM_6358_GPIO_BASE (0xfffe0080) #define BCM_6358_SPI_BASE (0xfffe0800) @@ -74,7 +74,15 @@ Signed-off-by: Jonas Gorski <[email protected]> #define BCM_6358_UDC0_BASE (0xfffe0800) #define BCM_6358_OHCI0_BASE (0xfffe1400) #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) -@@ -407,6 +414,7 @@ enum bcm63xx_regs_set { +@@ -420,6 +427,7 @@ enum bcm63xx_regs_set { + #define BCM_6362_UART1_BASE (0xb0000120) + #define BCM_6362_GPIO_BASE (0xb0000080) + #define BCM_6362_SPI_BASE (0xb0000800) ++#define BCM_6362_HSSPI_BASE (0xb0001000) + #define BCM_6362_UDC0_BASE (0xdeadbeef) + #define BCM_6362_OHCI0_BASE (0xb0002600) + #define BCM_6362_OHCI_PRIV_BASE (0xdeadbeef) +@@ -463,6 +471,7 @@ enum bcm63xx_regs_set { #define BCM_6368_UART1_BASE (0xb0000120) #define BCM_6368_GPIO_BASE (0xb0000080) #define BCM_6368_SPI_BASE (0xb0000800) @@ -82,7 +90,7 @@ Signed-off-by: Jonas Gorski <[email protected]> #define BCM_6368_UDC0_BASE (0xdeadbeef) #define BCM_6368_OHCI0_BASE (0xb0001600) #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) -@@ -456,6 +464,7 @@ extern const unsigned long *bcm63xx_regs +@@ -512,6 +521,7 @@ extern const unsigned long *bcm63xx_regs __GEN_RSET_BASE(__cpu, UART1) \ __GEN_RSET_BASE(__cpu, GPIO) \ __GEN_RSET_BASE(__cpu, SPI) \ @@ -90,7 +98,7 @@ Signed-off-by: Jonas Gorski <[email protected]> __GEN_RSET_BASE(__cpu, UDC0) \ __GEN_RSET_BASE(__cpu, OHCI0) \ __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ -@@ -497,6 +506,7 @@ extern const unsigned long *bcm63xx_regs +@@ -553,6 +563,7 @@ extern const unsigned long *bcm63xx_regs [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ @@ -98,7 +106,7 @@ Signed-off-by: Jonas Gorski <[email protected]> [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ -@@ -569,6 +579,7 @@ enum bcm63xx_irq { +@@ -628,6 +639,7 @@ enum bcm63xx_irq { IRQ_ENET0, IRQ_ENET1, IRQ_ENET_PHY, @@ -106,7 +114,7 @@ Signed-off-by: Jonas Gorski <[email protected]> IRQ_OHCI0, IRQ_EHCI0, IRQ_ENET0_RXDMA, -@@ -604,6 +615,7 @@ enum bcm63xx_irq { +@@ -663,6 +675,7 @@ enum bcm63xx_irq { #define BCM_6328_ENET0_IRQ 0 #define BCM_6328_ENET1_IRQ 0 #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) @@ -114,7 +122,7 @@ Signed-off-by: Jonas Gorski <[email protected]> #define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) #define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) #define BCM_6328_PCMCIA_IRQ 0 -@@ -642,6 +654,7 @@ enum bcm63xx_irq { +@@ -701,6 +714,7 @@ enum bcm63xx_irq { #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) #define BCM_6338_ENET1_IRQ 0 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) @@ -122,7 +130,7 @@ Signed-off-by: Jonas Gorski <[email protected]> #define BCM_6338_OHCI0_IRQ 0 #define BCM_6338_EHCI0_IRQ 0 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) -@@ -673,6 +686,7 @@ enum bcm63xx_irq { +@@ -732,6 +746,7 @@ enum bcm63xx_irq { #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) #define BCM_6345_ENET1_IRQ 0 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) @@ -130,7 +138,7 @@ Signed-off-by: Jonas Gorski <[email protected]> #define BCM_6345_OHCI0_IRQ 0 #define BCM_6345_EHCI0_IRQ 0 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) -@@ -704,6 +718,7 @@ enum bcm63xx_irq { +@@ -763,6 +778,7 @@ enum bcm63xx_irq { #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) @@ -138,7 +146,7 @@ Signed-off-by: Jonas Gorski <[email protected]> #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) #define BCM_6348_EHCI0_IRQ 0 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) -@@ -735,6 +750,7 @@ enum bcm63xx_irq { +@@ -794,6 +810,7 @@ enum bcm63xx_irq { #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) @@ -146,7 +154,15 @@ Signed-off-by: Jonas Gorski <[email protected]> #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) -@@ -775,6 +791,7 @@ enum bcm63xx_irq { +@@ -829,6 +846,7 @@ enum bcm63xx_irq { + #define BCM_6362_UART0_IRQ (IRQ_INTERNAL_BASE + 3) + #define BCM_6362_UART1_IRQ (IRQ_INTERNAL_BASE + 4) + #define BCM_6362_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8) ++#define BCM_6362_HSSPI_IRQ (IRQ_INTERNAL_BASE + 5) + #define BCM_6362_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) + #define BCM_6362_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) + #define BCM_6362_DSL_IRQ 0 +@@ -873,6 +891,7 @@ enum bcm63xx_irq { #define BCM_6368_ENET0_IRQ 0 #define BCM_6368_ENET1_IRQ 0 #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) @@ -154,7 +170,7 @@ Signed-off-by: Jonas Gorski <[email protected]> #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) #define BCM_6368_PCMCIA_IRQ 0 -@@ -815,6 +832,7 @@ extern const int *bcm63xx_irqs; +@@ -913,6 +932,7 @@ extern const int *bcm63xx_irqs; [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \ [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \ [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ @@ -174,7 +190,7 @@ Signed-off-by: Jonas Gorski <[email protected]> #endif /* BCM63XX_DEV_HSSPI_H */ --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h -@@ -1276,4 +1276,51 @@ +@@ -1356,4 +1356,51 @@ #define PCIE_DEVICE_OFFSET 0x8000 diff --git a/target/linux/brcm63xx/patches-3.3/420-MIPS-BCM63XX-Register-SPI-flash-if-present.patch b/target/linux/brcm63xx/patches-3.3/420-MIPS-BCM63XX-Register-SPI-flash-if-present.patch index f83dbcf..2b289b0 100644 --- a/target/linux/brcm63xx/patches-3.3/420-MIPS-BCM63XX-Register-SPI-flash-if-present.patch +++ b/target/linux/brcm63xx/patches-3.3/420-MIPS-BCM63XX-Register-SPI-flash-if-present.patch @@ -53,8 +53,16 @@ Signed-off-by: Jonas Gorski <[email protected]> val = bcm_misc_readl(MISC_STRAPBUS_6328_REG); if (val & STRAPBUS_6328_BOOT_SEL_SERIAL) return BCM63XX_FLASH_TYPE_SERIAL; -@@ -78,6 +97,9 @@ static int __init bcm63xx_detect_flash_t +@@ -77,6 +96,7 @@ static int __init bcm63xx_detect_flash_t + else return BCM63XX_FLASH_TYPE_SERIAL; + case BCM6362_CPU_ID: ++ bcm63xx_spi_flash_info[0].max_speed_hz = 40000000; + val = bcm_misc_readl(MISC_STRAPBUS_6362_REG); + if (val & STRAPBUS_6362_BOOT_SEL_SERIAL) + return BCM63XX_FLASH_TYPE_SERIAL; +@@ -84,6 +104,9 @@ static int __init bcm63xx_detect_flash_t + return BCM63XX_FLASH_TYPE_NAND; case BCM6368_CPU_ID: val = bcm_gpio_readl(GPIO_STRAPBUS_REG); + if (val & STRAPBUS_6368_SPI_CLK_FAST) @@ -63,13 +71,13 @@ Signed-off-by: Jonas Gorski <[email protected]> switch (val & STRAPBUS_6368_BOOT_SEL_MASK) { case STRAPBUS_6368_BOOT_SEL_NAND: return BCM63XX_FLASH_TYPE_NAND; -@@ -109,8 +131,11 @@ int __init bcm63xx_flash_register(void) +@@ -115,8 +138,11 @@ int __init bcm63xx_flash_register(void) return platform_device_register(&mtd_dev); case BCM63XX_FLASH_TYPE_SERIAL: - pr_warn("unsupported serial flash detected\n"); - return -ENODEV; -+ if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) + bcm63xx_flash_data.max_transfer_len = HS_SPI_BUFFER_LEN; + + return spi_register_board_info(bcm63xx_spi_flash_info, @@ -79,7 +87,7 @@ Signed-off-by: Jonas Gorski <[email protected]> return -ENODEV; --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h -@@ -555,6 +555,7 @@ +@@ -625,6 +625,7 @@ #define GPIO_STRAPBUS_REG 0x40 #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) diff --git a/target/linux/brcm63xx/patches-3.3/427-MTD-m25p80-allow-passing-pp_data.patch b/target/linux/brcm63xx/patches-3.3/427-MTD-m25p80-allow-passing-pp_data.patch index 51836f5..e27663b 100644 --- a/target/linux/brcm63xx/patches-3.3/427-MTD-m25p80-allow-passing-pp_data.patch +++ b/target/linux/brcm63xx/patches-3.3/427-MTD-m25p80-allow-passing-pp_data.patch @@ -19,7 +19,7 @@ Subject: [PATCH 65/79] MIPS: BCM63XX: store the flash type in global variable static struct mtd_partition mtd_partitions[] = { { .name = "cfe", -@@ -81,20 +83,23 @@ static int __init bcm63xx_detect_flash_t +@@ -81,27 +83,31 @@ static int __init bcm63xx_detect_flash_t bcm63xx_spi_flash_info[0].max_speed_hz = 40000000; val = bcm_misc_readl(MISC_STRAPBUS_6328_REG); if (val & STRAPBUS_6328_BOOT_SEL_SERIAL) @@ -45,10 +45,20 @@ Subject: [PATCH 65/79] MIPS: BCM63XX: store the flash type in global variable - return BCM63XX_FLASH_TYPE_SERIAL; + bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_SERIAL; + break; + case BCM6362_CPU_ID: + bcm63xx_spi_flash_info[0].max_speed_hz = 40000000; + val = bcm_misc_readl(MISC_STRAPBUS_6362_REG); + if (val & STRAPBUS_6362_BOOT_SEL_SERIAL) +- return BCM63XX_FLASH_TYPE_SERIAL; ++ bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_SERIAL; + else +- return BCM63XX_FLASH_TYPE_NAND; ++ bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_NAND; ++ break; case BCM6368_CPU_ID: val = bcm_gpio_readl(GPIO_STRAPBUS_REG); if (val & STRAPBUS_6368_SPI_CLK_FAST) -@@ -102,25 +107,32 @@ static int __init bcm63xx_detect_flash_t +@@ -109,25 +115,32 @@ static int __init bcm63xx_detect_flash_t switch (val & STRAPBUS_6368_BOOT_SEL_MASK) { case STRAPBUS_6368_BOOT_SEL_NAND: @@ -87,7 +97,7 @@ Subject: [PATCH 65/79] MIPS: BCM63XX: store the flash type in global variable case BCM63XX_FLASH_TYPE_PARALLEL: /* read base address of boot chip select (0) */ val = bcm_mpi_readl(MPI_CSBASE_REG(0)); -@@ -141,7 +153,7 @@ int __init bcm63xx_flash_register(void) +@@ -148,7 +161,7 @@ int __init bcm63xx_flash_register(void) return -ENODEV; default: pr_err("flash detection failed for BCM%x: %d", diff --git a/target/linux/brcm63xx/patches-3.3/430-MIPS-BCM63XX-pass-caldata-info-to-flash.patch b/target/linux/brcm63xx/patches-3.3/430-MIPS-BCM63XX-pass-caldata-info-to-flash.patch index 0a406fa..54756e5 100644 --- a/target/linux/brcm63xx/patches-3.3/430-MIPS-BCM63XX-pass-caldata-info-to-flash.patch +++ b/target/linux/brcm63xx/patches-3.3/430-MIPS-BCM63XX-pass-caldata-info-to-flash.patch @@ -46,7 +46,7 @@ Subject: [PATCH 69/80] MIPS: BCM63XX: pass caldata info to flash }; static struct spi_board_info bcm63xx_spi_flash_info[] = { -@@ -125,10 +129,13 @@ static int __init bcm63xx_detect_flash_t +@@ -133,10 +137,13 @@ static int __init bcm63xx_detect_flash_t return 0; } diff --git a/target/linux/brcm63xx/patches-3.3/511-board_V2500V.patch b/target/linux/brcm63xx/patches-3.3/511-board_V2500V.patch index 376b57e..8d2b6f9 100644 --- a/target/linux/brcm63xx/patches-3.3/511-board_V2500V.patch +++ b/target/linux/brcm63xx/patches-3.3/511-board_V2500V.patch @@ -106,7 +106,7 @@ #include <bcm63xx_cpu.h> #include <bcm63xx_dev_flash.h> #include <bcm63xx_dev_hsspi.h> -@@ -145,6 +146,13 @@ int __init bcm63xx_flash_register(int nu +@@ -153,6 +154,13 @@ int __init bcm63xx_flash_register(int nu val = bcm_mpi_readl(MPI_CSBASE_REG(0)); val &= MPI_CSBASE_BASE_MASK; diff --git a/target/linux/brcm63xx/patches-3.3/801-ssb_export_fallback_sprom.patch b/target/linux/brcm63xx/patches-3.3/801-ssb_export_fallback_sprom.patch index df3dc91..a1d441f 100644 --- a/target/linux/brcm63xx/patches-3.3/801-ssb_export_fallback_sprom.patch +++ b/target/linux/brcm63xx/patches-3.3/801-ssb_export_fallback_sprom.patch @@ -8,7 +8,7 @@ #include <linux/spi/spi.h> #include <linux/spi/spi_gpio.h> #include <linux/spi/74x164.h> -@@ -2652,7 +2653,7 @@ static void __init nb4_nvram_fixup(void) +@@ -2685,7 +2686,7 @@ static void __init nb4_nvram_fixup(void) * bcm4318 WLAN work */ #ifdef CONFIG_SSB_PCIHOST @@ -17,7 +17,7 @@ .revision = 0x02, .board_rev = 0x17, .country_code = 0x0, -@@ -2672,6 +2673,7 @@ static struct ssb_sprom bcm63xx_sprom = +@@ -2705,6 +2706,7 @@ static struct ssb_sprom bcm63xx_sprom = .boardflags_lo = 0x2848, .boardflags_hi = 0x0000, }; -- 1.7.10
>From b60fddf70767fae01b1764f644d8102dce84b17e Mon Sep 17 00:00:00 2001 From: Miguel GAIO <[email protected]> Date: Tue, 12 Jun 2012 15:49:09 +0200 Subject: [PATCH 2/2] * Add nb6 support BCM6362 board basee --- .../linux/brcm63xx/patches-3.3/554-board_nb6.patch | 61 ++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 target/linux/brcm63xx/patches-3.3/554-board_nb6.patch diff --git a/target/linux/brcm63xx/patches-3.3/554-board_nb6.patch b/target/linux/brcm63xx/patches-3.3/554-board_nb6.patch new file mode 100644 index 0000000..7653292 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.3/554-board_nb6.patch @@ -0,0 +1,61 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -2428,6 +2428,35 @@ static struct board_info __initdata boar + }; + #endif + ++#ifdef CONFIG_BCM63XX_CPU_6362 ++static struct board_info __initdata board_nb6 = { ++ .name = "NB6", ++ .expected_cpu_id = 0x6362, ++ ++ .has_uart0 = 1, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .buttons = { ++ { ++ .desc = "reset", ++ .gpio = 24, ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ { ++ .desc = "wps", ++ .gpio = 25, ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL, ++ }, ++ }, ++}; ++#endif ++ + /* + * known 6368 boards + */ +@@ -2624,6 +2653,10 @@ static const struct board_info __initdat + &board_spw303v, + #endif + ++#ifdef CONFIG_BCM63XX_CPU_6362 ++ &board_nb6, ++#endif ++ + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, + &board_96368mvngr, +@@ -2698,6 +2731,11 @@ static void __init boardid_fixup(u8 *boo + struct bcm_tag *tag = (struct bcm_tag *)(boot_addr + CFE_OFFSET_64K); + char *board_name = (char *)bcm63xx_nvram_get_name(); + ++ if (BCMCPU_IS_6362() && (!strncmp(board_name, "NB6-", sizeof("NB6-") - 1))) { ++ board_name[sizeof("NB6") - 1] = '\0'; ++ return ; ++ } ++ + /* check if bcm_tag is at 64k offset */ + if (strncmp(board_name, tag->boardid, BOARDID_LEN) != 0) { + /* else try 128k */ -- 1.7.10
_______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/mailman/listinfo/openwrt-devel
