On 06/27/2012 04:11 PM, Luka Perkov wrote:
Hi Wojciech,
On Wed, Jun 27, 2012 at 02:17:32PM +0200, Wojciech Dubowik wrote:
I have tested it on iconnect and it works from NAND. Older version
used to work from openocd but new one doesn't.
Can you please explain how did you test old version with OpenOCD?
I have used attached board config for openocd. Just use
iconnect_load_uboot function after connecting the board.
As far as I know, u-boot shouldn't work becasue you need
to set sys base so that it doesn't relocate. Maybe new one works
differently and you need to recompile it with different sys base
or some other compile flag.
I could have a look but at the moment I am really busy.
Br,
Wojtek
Maybe there is problem somewhere in configuration.
U-Boot 2012.04.01 (Jun 27 2012 - 14:11:30) Iomega iConnect Wireless
SoC: Kirkwood 88F6281_A0
DRAM: 256 MiB
WARNING: Caches not enabled
NAND: 512 MiB
In: serial
Out: serial
Err: serial
Net: egiga0
Hit any key to stop autoboot: 0
iconnect => ping 192.168.1.3
Using egiga0 device
host 192.168.1.3 is alive
iconnect => reset
resetting ...
Thank you for testing. We'll do something about the upgrade soon.
Luka
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# iomega Iconnect
# based on sheevaplug/dockstar
source [find target/feroceon.cfg]
jtag_rclk 6000
$_TARGETNAME configure \
-work-area-phys 0x10000000 \
-work-area-size 65536 \
-work-area-backup 0
# Disabled for the dockstar
#arm7_9 dcc_downloads enable
# this assumes the hardware default peripherals location before u-Boot moves it
set _FLASHNAME $_CHIPNAME.flash
nand device $_FLASHNAME orion 0 0xd8000000
proc iconnect_init { } {
# We need to assert DBGRQ while holding nSRST down.
# However DBGACK will be set only when nSRST is released.
# Furthermore, the JTAG interface doesn't respond at all when
# the CPU is in the WFI (wait for interrupts) state, so it is
# possible that initial tap examination failed. So let's
# re-examine the target again here when nSRST is asserted which
# should then succeed.
jtag_reset 0 1
feroceon.cpu arp_examine
halt 0
jtag_reset 0 0
wait_halt
arm mcr 15 0 0 1 0 0x00052078
#iconnect
mww phys 0xD0001400 0x43000400
mww phys 0xD0001404 0x36343040
mww phys 0xD0001408 0x1101333b
mww phys 0xD000140C 0x00000034
mww phys 0xD0001410 0x000000cc
mww phys 0xD0001414 0x00000000
mww phys 0xD0001418 0x00000000
mww phys 0xD000141C 0x00000642
mww phys 0xD0001420 0x00000004
mww phys 0xD0001424 0x0000F07F
mww phys 0xD0001428 0x00074410
mww phys 0xD000147c 0x00007441
# 1st bank is 128 MB
mww phys 0xD0001504 0x07FFFFF1
# 2nd bank is 128 MB
mww phys 0xD0001508 0x10000000
mww phys 0xD000150C 0x07FFFFF5
mww phys 0xD0001514 0x00000000
mww phys 0xD000151C 0x00000000
mww phys 0xD0001494 0x00120012
mww phys 0xD0001498 0x00000000
mww phys 0xD000149C 0x0000E40F
mww phys 0xD0001480 0x00000001
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0020204 0x00000000
mww phys 0xD0010000 0x01111111
mww phys 0xD0010004 0x11113322
mww phys 0xD0010008 0x00001111
mww phys 0xD0010418 0x003E07CF
mww phys 0xD001041C 0x000F0F0F
mww phys 0xD0010470 0x01C7D941
}
proc iconnect_load_uboot { } {
# load u-Boot into RAM and execute it
iconnect_init
load_image openwrt-kirkwood-iconnect-u-boot.kwb 0x800000
#verify_image openwrt-kirkwood-iconnect-u-boot.kwb 0x800000
resume 0x800200
}
proc iconnect_reset_cpu { } {
# System and User mode registers
# r0: 00000000 r1: 00000000 r2: 00000000 r3:
00000000
# r4: 00000000 r5: 00000000 r6: 00000000 r7:
00000000
# r8: 00000000 r9: 00000000 r10: 00000000 r11:
00000000
# r12: 00000000 sp_usr: 7dddee86 lr_usr: dffebe46 pc:
ffff0a42
# cpsr: 400000f3
reg r1 0
reg r2 0
reg r3 0
reg r4 0
reg r5 0
reg r6 0
reg r7 0
reg r8 0
reg r9 0
reg r10 0
reg r11 0
reg r12 0
reg sp_usr 0
reg lr_usr 0
reg pc 0
# Set the CPU in Supervisor mode
reg cpsr 0x13
# FIQ mode shadow registers
# r8_fiq: fbcfff64 r9_fiq: d7dfafd6 r10_fiq: 1fff6d2e r11_fiq:
1db65df4
# r12_fiq: ff5a6de4 sp_fiq: 745fe7d5 lr_fiq: 89f7ae3e spsr_fiq:
00000000
reg r8_fiq 0
reg r9_fiq 0
reg r10_fiq 0
reg r11_fiq 0
reg r12_fiq 0
reg sp_fiq 0
reg lr_fiq 0
reg spsr_fiq 0
# Supervisor mode shadow registers
# sp_svc: fffeff84 lr_svc: ffff0a43 spsr_svc: 00000000
reg sp_svc 0
reg lr_svc 0
reg spsr_svc 0
# Abort mode shadow registers
# sp_abt: 51fe66f7 lr_abt: d7abaef7 spsr_abt: 00000000
reg sp_abt 0
reg lr_abt 0
reg spsr_abt 0
# IRQ mode shadow registers
# sp_irq: 7fdb4ed5 lr_irq: 6d41122e spsr_irq: 00000000
reg sp_irq 0
reg lr_irq 0
reg spsr_irq 0
# Undefined instruction mode shadow registers
# sp_und: 75ffef7e lr_und: d75b6cd1 spsr_und: 00000000
reg sp_und 0
reg lr_und 0
reg spsr_und 0
}
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