Missing ETOP initialization
When using brnboot instead of u-boot for booting OpenWRT, no network
initialization is done by the bootloader. Adapt missing register
writes from uboot-lantiq ifx_etop.c lq_eth_init_chip().
Controversial part, but seems to be required for ethernet to work on
W502V:
+-#define ETOP_MII_NORMAL 0xd
+-#define ETOP_MII_REVERSE 0xe
++#define ETOP_MII_NORMAL 0x8
++#define ETOP_MII_REVERSE 0xa
See lq_eth_init_chip():
#ifdef CONFIG_RMII
*ETOP_CFG = (*ETOP_CFG & 0xFFFFFFFC) | 0x0000000A;
#else
*ETOP_CFG = (*ETOP_CFG & 0xFFFFFFFC) | 0x00000008;
#endif
(Which is a bit buggy itself, the mask should be 0xFFFFFFF0 or 0xFFFFFFF4,
it clearly sets bit 3 as well in addition to touching bits 0 and 1)
Note that ETOP_CFG is one of the registers where my previous patch changes the
register offset, so it's likely that the lantiq_etop driver never affected
the reverse/normal mii setting and was relying on uboot to set this.
Signed-off-by: Tobias Diedrich <[email protected]>
Index: target/linux/lantiq/patches-3.3/0027-etop-without-uboot.patch
===================================================================
--- target/linux/lantiq/patches-3.3/0027-etop-without-uboot.patch
(revision 0)
+++ target/linux/lantiq/patches-3.3/0027-etop-without-uboot.patch
(working copy)
@@ -0,0 +1,43 @@
+Index: linux-3.3.8/drivers/net/ethernet/lantiq_etop.c
+===================================================================
+--- linux-3.3.8.orig/drivers/net/ethernet/lantiq_etop.c 2012-08-04
23:21:41.040574994 +0200
++++ linux-3.3.8/drivers/net/ethernet/lantiq_etop.c 2012-08-04
23:23:32.557037752 +0200
+@@ -44,6 +44,7 @@
+ #include <xway_dma.h>
+ #include <lantiq_platform.h>
+
++#define LTQ_ETOP_MDIO_CFG 0x11800
+ #define LTQ_ETOP_MDIO 0x11804
+ #define MDIO_REQUEST 0x80000000
+ #define MDIO_READ 0x40000000
+@@ -68,8 +69,8 @@
+
+ #define ETOP_FTCU BIT(28)
+ #define ETOP_MII_MASK 0xf
+-#define ETOP_MII_NORMAL 0xd
+-#define ETOP_MII_REVERSE 0xe
++#define ETOP_MII_NORMAL 0x8
++#define ETOP_MII_REVERSE 0xa
+ #define ETOP_PLEN_UNDER 0x40
+ #define ETOP_CFG_MII0 0x01
+
+@@ -325,6 +326,10 @@
+
+ clk_enable(priv->clk_ppe);
+
++ /* From uboot-lantiq ifx_etop.c lq_eth_init_chip() */
++ ltq_etop_w32_mask(0x6, 0, LTQ_ETOP_MDIO_CFG);
++ ltq_etop_w32(0x187, LTQ_ETOP_MAC_CFG);
++
+ if (ltq_has_gbit()) {
+ ltq_etop_gbit_init(dev);
+ /* force the etops link to the gbit to MII */
+@@ -361,7 +366,7 @@
+ }
+
+ /* enable crc generation */
+- ltq_etop_w32(ETOP_CGEN, LTQ_ETOP_MAC_CFG);
++ ltq_etop_w32_mask(ETOP_CGEN, ETOP_CGEN, LTQ_ETOP_MAC_CFG);
+
+ return 0;
+ }
--
Tobias PGP: http://8ef7ddba.uguu.de
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