Insure that remaining cores are assigned the shared IRQ (MIPS IRQ0) when
the non-shared IRQs have all been assigned. ChipCommon and I2S cores should
always be assigned the shared IRQ.
Note: I did not include a "default" case for assigning all other cores to the
shared IRQ, as it caused the DDR1/DDR2 Memory Controller core to be
assigned to IRQ2 and resulted in a never ending stack dump. If this
is to be pursued, I would recommend a separate patch.
Signed-off-by: Nathan Hintz <[email protected]>
--- /dev/null
+++ target/linux/brcm47xx/patches-3.6/238-bcma-shared-irq-update.patch
@@ -0,0 +1,19 @@
+--- a/drivers/bcma/driver_mips.c
++++ b/drivers/bcma/driver_mips.c
+@@ -315,9 +315,15 @@ void bcma_core_mips_init(struct bcma_drv
+ /* These devices get their own IRQ line if available,
+ * the rest goes on IRQ0
+ */
+- if (mcore->assigned_irqs <= 4)
++ if (mcore->assigned_irqs <= 4) {
+ bcma_core_mips_set_irq(core,
+ mcore->assigned_irqs++);
++ break;
++ }
++ /* fallthrough */
++ case BCMA_CORE_CHIPCOMMON:
++ case BCMA_CORE_I2S:
++ bcma_core_mips_set_irq(core, 0);
+ break;
+ }
+ }
_______________________________________________
openwrt-devel mailing list
[email protected]
https://lists.openwrt.org/mailman/listinfo/openwrt-devel
