This makes the PCI bus topology more standard for devices behind a bridge
Signed-off-by: Tim Harvey <[email protected]>
---
.../patches-3.3/066-pcie_bus_topology.patch | 27 ++++++++++++++++++++
1 files changed, 27 insertions(+), 0 deletions(-)
create mode 100644 target/linux/cns3xxx/patches-3.3/066-pcie_bus_topology.patch
diff --git a/target/linux/cns3xxx/patches-3.3/066-pcie_bus_topology.patch
b/target/linux/cns3xxx/patches-3.3/066-pcie_bus_topology.patch
new file mode 100644
index 0000000..269a0fb
--- /dev/null
+++ b/target/linux/cns3xxx/patches-3.3/066-pcie_bus_topology.patch
@@ -0,0 +1,27 @@
+--- a/arch/arm/mach-cns3xxx/pcie.c
++++ b/arch/arm/mach-cns3xxx/pcie.c
+@@ -79,9 +79,11 @@ static void __iomem *cns3xxx_pci_cfg_bas
+ * the first device on the same bus as the CNS PCI bridge.
+ */
+ if (busno == 0) {
+- if (slot > 1)
++ if (slot > 0)
+ return NULL;
+ type = slot;
++ } else if (busno == 1) {
++ type = CNS3XXX_CFG0_TYPE;
+ } else {
+ type = CNS3XXX_CFG1_TYPE;
+ }
+@@ -428,8 +430,9 @@ static void __init cns3xxx_pcie_hw_init(
+ if (!cnspci->linked)
+ return;
+
+- /* Set Device Max_Read_Request_Size to 128 byte */
+- devfn = PCI_DEVFN(1, 0);
++ /* Configure Root Complex: Set Device Max_Read_Request_Size to 128 byte
*/
++ bus.number = 1;
++ devfn = PCI_DEVFN(0, 0);
+ pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
+ pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
+ dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */
--
1.7.5.4
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