Hi there,
I'm currently trying to figure out a way how to solve the following
issue elegantly (i.e. from the mach file):
Target Device: WD My Net N750 (AR9344 based, with AR8327N switch)
Problem:
The device powers down all the PHYs from within the bootloader (possibly
to prevent early LAN <-> WAN leakage, as the ports are on the same
switch and separated by VLANs only).
The PHYs are powered down by writing 0x800 (Set Bit 11 (POWER_DOWN) to
1) to register 0x0 of each PHY from within the bootloader.
The PHYs cannot be read while powered down (but can be written). This
results in mdiobus_scan (drivers/net/phy/mdio_bus.c) reading bogus PHY IDs.
Solution:
Power all PHYs back up by writing 0x1000 (Set Bit 12 (AUTO_
NEGOTIATION) to 1) to register 0x0 of each PHY _before_ scanning the
MDIO bus for PHY IDs but _after_ resetting/initializing the bus.
I have attached a patch that works (but is a nasty hack).
So now I have the question how to handle this in a way that would also
be acceptable for upstream.
I was hoping for some input from the ar71xx gurus on how to do this :)
Thanks,
Felix
--- drivers/net/phy/mdio_bus.c.orig 2013-12-09 14:11:13.693202164 +0100
+++ drivers/net/phy/mdio_bus.c 2013-12-09 14:12:23.922744357 +0100
@@ -164,6 +164,10 @@
if (bus->reset)
bus->reset(bus);
+ for (i = 0; i < PHY_MAX_ADDR; i++)
+ mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+ msleep(1000);
+
for (i = 0; i < PHY_MAX_ADDR; i++) {
if ((bus->phy_mask & (1 << i)) == 0) {
struct phy_device *phydev;
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