I have a feeling that the patch posted by luka will fix the fritz3370
problem.
i have a vague recollection that it worked once upon a time. I also
remember that in my last test it did not work, but i had wifi enabled so
that would fit in with the missing locking.
I'll let you know if that is the case and then we can look at the
nor/nand/pci combo afterwards
John
On 22/01/2014 09:46, Ben Mulvihill wrote:
> I missed that one on the mailing list. It is the same fix,
> or part of it anyway.
>
> Ben
>
> On Wed, 2014-01-22 at 01:01 +0100, Luka Perkov wrote:
>> On Tue, Jan 21, 2014 at 08:50:03PM +0100, Ben Mulvihill wrote:
>>> Any enlightenment you can provide will be gratefully received.
>> I have not tested this patch yet but it could be related to your
>> problem...
>>
>> Luka
>>
>>
>> From ad77bb90cbebcd107e81722e1fbdcff91fe55614 Mon Sep 17 00:00:00 2001
>> From: Antonios Vamporakis <[email protected]>
>> Date: Sun, 29 Dec 2013 23:40:15 +0100
>> Subject: [PATCH 03/14] lantiq: resolve EBU conflict between NAND and PCI
>>
>> Stop PCI IRQs from taking over the EBU wile NAND is accessed.
>>
>> Signed-off-by: Antonios Vamporakis <[email protected]>
>> ---
>> .../0203-xway-fix-nand-pci-conflict.patch | 19
>> +++++++++++++++++++
>> 1 file changed, 19 insertions(+)
>> create mode 100644
>> target/linux/lantiq/patches-3.10/0203-xway-fix-nand-pci-conflict.patch
>>
>> diff --git
>> a/target/linux/lantiq/patches-3.10/0203-xway-fix-nand-pci-conflict.patch
>> b/target/linux/lantiq/patches-3.10/0203-xway-fix-nand-pci-conflict.patch
>> new file mode 100644
>> index 0000000..f4b5793
>> --- /dev/null
>> +++ b/target/linux/lantiq/patches-3.10/0203-xway-fix-nand-pci-conflict.patch
>> @@ -0,0 +1,19 @@
>> +--- a/drivers/mtd/nand/xway_nand.c
>> ++++ b/drivers/mtd/nand/xway_nand.c
>> +@@ -80,13 +80,16 @@ static void xway_reset_chip(struct nand_
>> +
>> + static void xway_select_chip(struct mtd_info *mtd, int chip)
>> + {
>> ++ static unsigned long csflags;
>> +
>> + switch (chip) {
>> + case -1:
>> + ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
>> + ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
>> ++ spin_unlock_irqrestore(&ebu_lock, csflags);
>> + break;
>> + case 0:
>> ++ spin_lock_irqsave(&ebu_lock, csflags);
>> + ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
>> + ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
>> + break;
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