Citeren Paul Fertser <fercer...@gmail.com>:
Arjen de Korte <arjen+open...@de-korte.org> writes:
Citeren Paul Fertser <fercer...@gmail.com>:
Another is
that such a patch is mostly a bad substitute for proper hardware design.
Not really. There may not be a hardware reset line if the flash is
running in x4 data mode.
Imagine there's a bug in the kernel that made it hang for real. Then
you're counting on the watchdog (usually SoCs come with one integrated)
to cleanly reboot the whole system. If the flash is used in QSPI or
whatever other mode that doesn't allow a dedicated reset line then it
needs to be powercycled on hardware level to ensure reliable operation,
I think.
Exactly. If you're designing for rock bottom low cost (I'm a hardware
engineer), the SPI flash used will not have a dedicated reset line.
That is why helpdesks will always tell in case of problems to power
off a device for 30-60 seconds and then switch it back on again. In
many cases, a watchdog reset is not equivalent to a power on reset.
Best regards, Arjen
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