-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Weijie Gao <[email protected]> wrote: > Signed-off-by: Weijie Gao <[email protected]> > > According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz > input clock as the REF_CLK instead of 5MHz. > > The correct CPU PLL calculation procedure is as follows: > CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2. > > This patch is compatible with the current calculation procedure with > default > DIV and REF_DIV values. > > Test on both AR7240, AR7241 and AR7242.
So, what was the behaviour before? Cheers, Karl P -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAEBAgAGBQJV8ZUHAAoJEBmotQ/U1cr2aAAP/iPniiHKY/hEKqriniqdWdvE y9e9gs48KcYxBt5wHninUK1Jsz3Gc1qzpsuyfxxWS6yuZvqMeSnR1UBnH9ztbRQM ZvXKS79GhCEQkdBlZL74RBqVaBGz0lQ59La7b4NRTmPfKV5HQdZpo51EaA/iNOwT 6iy1w2HUEhGIlxG+/2NSz2ppNPeg82iexaxus70NrGtmtmttaUxMJ4hSFZ74ToMF zsPzn24GFGBrCSZpTQb5kHp+cz+ZO6SvANtCAsFjJBY4Wyo1To8K5/sOzOy/WY2m tzvOwrFnGWlnmAPATopSN5eWYcPK60HFUkCrtj/bMLfI3b3ses787Z5YBegZRkGe g15zWuSp/B7rRQFagyYw7UtuCaKZdHlvAvBfOA+nIZP9wMX16v1vy41MHhMoD39z 4ZLjvq3xavdVGMNlFKTn8C/qQEMNS1WDXjI3IhU98+CTlpTirauSE1xccTIEwUWs okEvhSWGoc8HsgSMuNLI2OdlzQk3QkLGujd1QSB3KNA5Jwwjldnc/wB8gt3/T3W1 U4sGr4omig3hyv0+MHtnlmlzeQH+earq8aykTdqT1odLHLZwoBqFqhQFcuzG1puS VsL0KhR2X4BeNFz8rDtfjJ6qS/SH8nrUmXil2/peqwXWWwTDAkwVCSu+9OZ8PfjN ppcYaXyAm55OeDDx8GmC =vE53 -----END PGP SIGNATURE-----
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