Hi, ok, I will split this patch into 2 patches:
[1/2] pinctrl/lantiq: split xway_mfp into dedicated tables [2/2] pinctrl/lantiq: adapt device-trees to new tables Would that be ok? To get the pinctrl patch upstream, we also have to send the 0012-pinctrl-lantiq-fix-up-pinmux.patch upstream. Should I do this in a patch series as well? To whom should this patch be sent? (maintainer/mailing-list?) Martin -----Ursprüngliche Nachricht----- Von: openwrt-devel [mailto:[email protected]] Im Auftrag von John Crispin Gesendet: Montag, 16. November 2015 10:50 An: [email protected] Betreff: Re: [OpenWrt-Devel] [PATCH] pinctrl/lantiq: split xway_mfp into dedicated tables Hi, the dts and kernel changes should be in separate patches. also please send the pinctrl patch upstream. John On 16/11/2015 10:42, Martin Schiller wrote: > This patch splits the inadequate "pinctrl-xway" and "pinctrl-xr9" settings > into dedicated "pinctrl-ase", "pinctrl-danube", "pinctrl-xrx100" and > "pinctrl-xrx200" configuration tables. > > Based on the newest Lantiq Hardware Description it turend out, that there are > some differences in the GPIO alternative functions of the Danube, xRX100 and > xRX200 families, which makes it impossible to use only one xway_mfp table. > > This patch is also the first step to add support for the xRX300 family. > > Signed-off-by: Martin Schiller <[email protected]> > --- > target/linux/lantiq/dts/BTHOMEHUBV2B.dts | 2 +- > target/linux/lantiq/dts/BTHOMEHUBV3A.dts | 2 +- > target/linux/lantiq/dts/EASY50712.dts | 2 +- > target/linux/lantiq/dts/EASY50810.dts | 2 +- > target/linux/lantiq/dts/EASY80920.dtsi | 2 +- > target/linux/lantiq/dts/GR7000.dts | 2 +- > target/linux/lantiq/dts/P2601HNFX.dts | 2 +- > target/linux/lantiq/dts/P2812HNUFX.dtsi | 2 +- > target/linux/lantiq/dts/VGV7519.dtsi | 2 +- > target/linux/lantiq/dts/ar9.dtsi | 2 +- > target/linux/lantiq/dts/danube.dtsi | 2 +- > target/linux/lantiq/dts/vr9.dtsi | 2 +- > .../patches-4.1/0150-lantiq-pinctrl-xway.patch | 1059 > +++++++++++++++++++- > 13 files changed, 1061 insertions(+), 22 deletions(-) > > diff --git a/target/linux/lantiq/dts/BTHOMEHUBV2B.dts > b/target/linux/lantiq/dts/BTHOMEHUBV2B.dts > index 9b3180c..e2d713e 100644 > --- a/target/linux/lantiq/dts/BTHOMEHUBV2B.dts > +++ b/target/linux/lantiq/dts/BTHOMEHUBV2B.dts > @@ -102,7 +102,7 @@ > }; > > gpio: pinmux@E100B10 { > -compatible = "lantiq,pinctrl-xway"; > +compatible = "lantiq,pinctrl-danube"; > pinctrl-names = "default"; > pinctrl-0 = <&state_default>; > > diff --git a/target/linux/lantiq/dts/BTHOMEHUBV3A.dts > b/target/linux/lantiq/dts/BTHOMEHUBV3A.dts > index 1ae9840..9383498 100644 > --- a/target/linux/lantiq/dts/BTHOMEHUBV3A.dts > +++ b/target/linux/lantiq/dts/BTHOMEHUBV3A.dts > @@ -79,7 +79,7 @@ > }; > > gpio: pinmux@E100B10 { > -compatible = "lantiq,pinctrl-xr9"; > +compatible = "lantiq,pinctrl-xrx100"; > pinctrl-names = "default"; > pinctrl-0 = <&state_default>; > > diff --git a/target/linux/lantiq/dts/EASY50712.dts > b/target/linux/lantiq/dts/EASY50712.dts > index e44267a..e0d5ed1 100644 > --- a/target/linux/lantiq/dts/EASY50712.dts > +++ b/target/linux/lantiq/dts/EASY50712.dts > @@ -51,7 +51,7 @@ > }; > > gpio: pinmux@E100B10 { > -compatible = "lantiq,pinctrl-xway"; > +compatible = "lantiq,pinctrl-danube"; > pinctrl-names = "default"; > pinctrl-0 = <&state_default>; > > diff --git a/target/linux/lantiq/dts/EASY50810.dts > b/target/linux/lantiq/dts/EASY50810.dts > index 5f4b733..73f31ea 100644 > --- a/target/linux/lantiq/dts/EASY50810.dts > +++ b/target/linux/lantiq/dts/EASY50810.dts > @@ -51,7 +51,7 @@ > }; > > gpio: pinmux@E100B10 { > -compatible = "lantiq,pinctrl-xr9"; > +compatible = "lantiq,pinctrl-xrx100"; > pinctrl-names = "default"; > pinctrl-0 = <&state_default>; > > diff --git a/target/linux/lantiq/dts/EASY80920.dtsi > b/target/linux/lantiq/dts/EASY80920.dtsi > index 4013610..0600d36 100644 > --- a/target/linux/lantiq/dts/EASY80920.dtsi > +++ b/target/linux/lantiq/dts/EASY80920.dtsi > @@ -71,7 +71,7 @@ > }; > > gpio: pinmux@E100B10 { > -compatible = "lantiq,pinctrl-xr9"; > +compatible = "lantiq,pinctrl-xrx200"; > pinctrl-names = "default"; > pinctrl-0 = <&state_default>; > > diff --git a/target/linux/lantiq/dts/GR7000.dts > b/target/linux/lantiq/dts/GR7000.dts > index fcc27eb..bc95f1f 100644 > --- a/target/linux/lantiq/dts/GR7000.dts > +++ b/target/linux/lantiq/dts/GR7000.dts > @@ -42,7 +42,7 @@ > }; > > gpio: pinmux@E100B10 { > -compatible = "lantiq,pinctrl-xr9"; > +compatible = "lantiq,pinctrl-xrx100"; > pinctrl-names = "default"; > pinctrl-0 = <&state_default>; > > diff --git a/target/linux/lantiq/dts/P2601HNFX.dts > b/target/linux/lantiq/dts/P2601HNFX.dts > index bb9193e..c22c547 100644 > --- a/target/linux/lantiq/dts/P2601HNFX.dts > +++ b/target/linux/lantiq/dts/P2601HNFX.dts > @@ -50,7 +50,7 @@ > }; > > gpio: pinmux@E100B10 { > -compatible = "lantiq,pinctrl-xr9"; > +compatible = "lantiq,pinctrl-xrx100"; > pinctrl-names = "default"; > pinctrl-0 = <&state_default>; > > diff --git a/target/linux/lantiq/dts/P2812HNUFX.dtsi > b/target/linux/lantiq/dts/P2812HNUFX.dtsi > index d93e862..1dd13ac 100644 > --- a/target/linux/lantiq/dts/P2812HNUFX.dtsi > +++ b/target/linux/lantiq/dts/P2812HNUFX.dtsi > @@ -25,7 +25,7 @@ > }; > > gpio: pinmux@E100B10 { > -compatible = "lantiq,pinctrl-xr9"; > +compatible = "lantiq,pinctrl-xrx200"; > pinctrl-names = "default"; > pinctrl-0 = <&state_default>; > > diff --git a/target/linux/lantiq/dts/VGV7519.dtsi > b/target/linux/lantiq/dts/VGV7519.dtsi > index 7a7fddb..587b79b 100644 > --- a/target/linux/lantiq/dts/VGV7519.dtsi > +++ b/target/linux/lantiq/dts/VGV7519.dtsi > @@ -26,7 +26,7 @@ > }; > > gpio: pinmux@E100B10 { > -compatible = "lantiq,pinctrl-xr9"; > +compatible = "lantiq,pinctrl-xrx200"; > pinctrl-names = "default"; > pinctrl-0 = <&state_default>; > > diff --git a/target/linux/lantiq/dts/ar9.dtsi > b/target/linux/lantiq/dts/ar9.dtsi > index ee4e374..f09d298 100644 > --- a/target/linux/lantiq/dts/ar9.dtsi > +++ b/target/linux/lantiq/dts/ar9.dtsi > @@ -101,7 +101,7 @@ > }; > > gpio: pinmux@E100B10 { > -compatible = "lantiq,pinctrl-xr9"; > +compatible = "lantiq,pinctrl-xrx100"; > #gpio-cells = <2>; > gpio-controller; > reg = <0xE100B10 0xA0>; > diff --git a/target/linux/lantiq/dts/danube.dtsi > b/target/linux/lantiq/dts/danube.dtsi > index 698196d..cbc4786 100644 > --- a/target/linux/lantiq/dts/danube.dtsi > +++ b/target/linux/lantiq/dts/danube.dtsi > @@ -123,7 +123,7 @@ > }; > > gpio: pinmux@E100B10 { > -compatible = "lantiq,pinctrl-xway"; > +compatible = "lantiq,pinctrl-danube"; > #gpio-cells = <2>; > gpio-controller; > reg = <0xE100B10 0xA0>; > diff --git a/target/linux/lantiq/dts/vr9.dtsi > b/target/linux/lantiq/dts/vr9.dtsi > index 136483a..130823d 100644 > --- a/target/linux/lantiq/dts/vr9.dtsi > +++ b/target/linux/lantiq/dts/vr9.dtsi > @@ -108,7 +108,7 @@ > }; > > gpio: pinmux@E100B10 { > -compatible = "lantiq,pinctrl-xr9"; > +compatible = "lantiq,pinctrl-xrx200"; > #gpio-cells = <2>; > gpio-controller; > reg = <0xE100B10 0xA0>; > diff --git a/target/linux/lantiq/patches-4.1/0150-lantiq-pinctrl-xway.patch > b/target/linux/lantiq/patches-4.1/0150-lantiq-pinctrl-xway.patch > index 84adbe6..3fc0432 100644 > --- a/target/linux/lantiq/patches-4.1/0150-lantiq-pinctrl-xway.patch > +++ b/target/linux/lantiq/patches-4.1/0150-lantiq-pinctrl-xway.patch > @@ -1,15 +1,1054 @@ > --- a/drivers/pinctrl/pinctrl-xway.c > +++ b/drivers/pinctrl/pinctrl-xway.c > -@@ -152,10 +152,10 @@ static const struct ltq_mfp_pin xway_mfp > - MFP_XWAY(GPIO41, GPIO,NONE,NONE,NONE), > - MFP_XWAY(GPIO42, GPIO,MDIO,NONE,NONE), > - MFP_XWAY(GPIO43, GPIO,MDIO,NONE,NONE), > +@@ -7,6 +7,7 @@ > + * publishhed by the Free Software Foundation. > + * > + * Copyright (C) 2012 John Crispin <[email protected]> > ++ * Copyright (C) 2015 Martin Schiller <[email protected]> > + */ > + > + #include <linux/err.h> > +@@ -80,17 +81,18 @@ > + #define FUNC_MUX(f, m)\ > + { .func = f, .mux = XWAY_MUX_##m, } > + > +-#define XWAY_MAX_PIN32 > +-#define XR9_MAX_PIN56 > +- > + enum xway_mux { > + XWAY_MUX_GPIO = 0, > + XWAY_MUX_SPI, > + XWAY_MUX_ASC, > ++XWAY_MUX_USIF, > + XWAY_MUX_PCI, > ++XWAY_MUX_CBUS, > + XWAY_MUX_CGU, > + XWAY_MUX_EBU, > ++XWAY_MUX_EBU2, > + XWAY_MUX_JTAG, > ++XWAY_MUX_MCD, > + XWAY_MUX_EXIN, > + XWAY_MUX_TDM, > + XWAY_MUX_STP, > +@@ -103,68 +105,12 @@ enum xway_mux { > + XWAY_MUX_DFE, > + XWAY_MUX_SDIO, > + XWAY_MUX_GPHY, > ++XWAY_MUX_SSI, > + XWAY_MUX_NONE = 0xffff, > + }; > + > +-static const struct ltq_mfp_pin xway_mfp[] = { > +-/* pin f0f1f2f3 */ > +-MFP_XWAY(GPIO0, GPIO,EXIN,NONE,TDM), > +-MFP_XWAY(GPIO1, GPIO,EXIN,NONE,NONE), > +-MFP_XWAY(GPIO2, GPIO,CGU,EXIN,GPHY), > +-MFP_XWAY(GPIO3, GPIO,CGU,NONE,PCI), > +-MFP_XWAY(GPIO4, GPIO,STP,NONE,ASC), > +-MFP_XWAY(GPIO5, GPIO,STP,NONE,GPHY), > +-MFP_XWAY(GPIO6, GPIO,STP,GPT,ASC), > +-MFP_XWAY(GPIO7, GPIO,CGU,PCI,GPHY), > +-MFP_XWAY(GPIO8, GPIO,CGU,NMI,NONE), > +-MFP_XWAY(GPIO9, GPIO,ASC,SPI,EXIN), > +-MFP_XWAY(GPIO10, GPIO,ASC,SPI,NONE), > +-MFP_XWAY(GPIO11, GPIO,ASC,PCI,SPI), > +-MFP_XWAY(GPIO12, GPIO,ASC,NONE,NONE), > +-MFP_XWAY(GPIO13, GPIO,EBU,SPI,NONE), > +-MFP_XWAY(GPIO14, GPIO,CGU,PCI,NONE), > +-MFP_XWAY(GPIO15, GPIO,SPI,JTAG,NONE), > +-MFP_XWAY(GPIO16, GPIO,SPI,NONE,JTAG), > +-MFP_XWAY(GPIO17, GPIO,SPI,NONE,JTAG), > +-MFP_XWAY(GPIO18, GPIO,SPI,NONE,JTAG), > +-MFP_XWAY(GPIO19, GPIO,PCI,NONE,NONE), > +-MFP_XWAY(GPIO20, GPIO,JTAG,NONE,NONE), > +-MFP_XWAY(GPIO21, GPIO,PCI,EBU,GPT), > +-MFP_XWAY(GPIO22, GPIO,SPI,NONE,NONE), > +-MFP_XWAY(GPIO23, GPIO,EBU,PCI,STP), > +-MFP_XWAY(GPIO24, GPIO,EBU,TDM,PCI), > +-MFP_XWAY(GPIO25, GPIO,TDM,NONE,ASC), > +-MFP_XWAY(GPIO26, GPIO,EBU,NONE,TDM), > +-MFP_XWAY(GPIO27, GPIO,TDM,NONE,ASC), > +-MFP_XWAY(GPIO28, GPIO,GPT,NONE,NONE), > +-MFP_XWAY(GPIO29, GPIO,PCI,NONE,NONE), > +-MFP_XWAY(GPIO30, GPIO,PCI,NONE,NONE), > +-MFP_XWAY(GPIO31, GPIO,EBU,PCI,NONE), > +-MFP_XWAY(GPIO32, GPIO,NONE,NONE,EBU), > +-MFP_XWAY(GPIO33, GPIO,NONE,NONE,EBU), > +-MFP_XWAY(GPIO34, GPIO,NONE,NONE,EBU), > +-MFP_XWAY(GPIO35, GPIO,NONE,NONE,EBU), > +-MFP_XWAY(GPIO36, GPIO,SIN,NONE,EBU), > +-MFP_XWAY(GPIO37, GPIO,PCI,NONE,NONE), > +-MFP_XWAY(GPIO38, GPIO,PCI,NONE,NONE), > +-MFP_XWAY(GPIO39, GPIO,EXIN,NONE,NONE), > +-MFP_XWAY(GPIO40, GPIO,NONE,NONE,NONE), > +-MFP_XWAY(GPIO41, GPIO,NONE,NONE,NONE), > +-MFP_XWAY(GPIO42, GPIO,MDIO,NONE,NONE), > +-MFP_XWAY(GPIO43, GPIO,MDIO,NONE,NONE), > -MFP_XWAY(GPIO44, GPIO,NONE,GPHY,SIN), > -+MFP_XWAY(GPIO44, GPIO,MII,SIN,GPHY), > - MFP_XWAY(GPIO45, GPIO,NONE,GPHY,SIN), > - MFP_XWAY(GPIO46, GPIO,NONE,NONE,EXIN), > +-MFP_XWAY(GPIO45, GPIO,NONE,GPHY,SIN), > +-MFP_XWAY(GPIO46, GPIO,NONE,NONE,EXIN), > -MFP_XWAY(GPIO47, GPIO,NONE,GPHY,SIN), > +-MFP_XWAY(GPIO48, GPIO,EBU,NONE,NONE), > +-MFP_XWAY(GPIO49, GPIO,EBU,NONE,NONE), > +-MFP_XWAY(GPIO50, GPIO,NONE,NONE,NONE), > +-MFP_XWAY(GPIO51, GPIO,NONE,NONE,NONE), > +-MFP_XWAY(GPIO52, GPIO,NONE,NONE,NONE), > +-MFP_XWAY(GPIO53, GPIO,NONE,NONE,NONE), > +-MFP_XWAY(GPIO54, GPIO,NONE,NONE,NONE), > +-MFP_XWAY(GPIO55, GPIO,NONE,NONE,NONE), > +-}; > ++/* --------- ase related code --------- */ > ++#define ASE_MAX_PIN32 > + > + static const struct ltq_mfp_pin ase_mfp[] = { > + /* pin f0f1f2f3 */ > +@@ -189,154 +135,48 @@ static const struct ltq_mfp_pin ase_mfp[ > + MFP_XWAY(GPIO18, GPIO,NONE,NONE,NONE), > + MFP_XWAY(GPIO19, GPIO,EBU,MII,SDIO), > + MFP_XWAY(GPIO20, GPIO,EBU,MII,SDIO), > +-MFP_XWAY(GPIO21, GPIO,EBU,MII,SDIO), > ++MFP_XWAY(GPIO21, GPIO,EBU,MII,EBU2), > + MFP_XWAY(GPIO22, GPIO,EBU,MII,CGU), > + MFP_XWAY(GPIO23, GPIO,EBU,MII,CGU), > +-MFP_XWAY(GPIO24, GPIO,EBU,NONE,MII), > ++MFP_XWAY(GPIO24, GPIO,EBU,EBU2,MDIO), > + MFP_XWAY(GPIO25, GPIO,EBU,MII,GPT), > + MFP_XWAY(GPIO26, GPIO,EBU,MII,SDIO), > +-MFP_XWAY(GPIO27, GPIO,EBU,NONE,MII), > ++MFP_XWAY(GPIO27, GPIO,EBU,NONE,MDIO), > + MFP_XWAY(GPIO28, GPIO,MII,EBU,SDIO), > + MFP_XWAY(GPIO29, GPIO,EBU,MII,EXIN), > + MFP_XWAY(GPIO30, GPIO,NONE,NONE,NONE), > + MFP_XWAY(GPIO31, GPIO,NONE,NONE,NONE), > + }; > + > +-static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, > GPIO35}; > +-static const unsigned pins_asc0[] = {GPIO11, GPIO12}; > +-static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10}; > +-static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6}; > +-static const unsigned pins_nmi[] = {GPIO8}; > +-static const unsigned pins_mdio[] = {GPIO42, GPIO43}; > +- > +-static const unsigned pins_gphy0_led0[] = {GPIO5}; > +-static const unsigned pins_gphy0_led1[] = {GPIO7}; > +-static const unsigned pins_gphy0_led2[] = {GPIO2}; > +-static const unsigned pins_gphy1_led0[] = {GPIO44}; > +-static const unsigned pins_gphy1_led1[] = {GPIO45}; > +-static const unsigned pins_gphy1_led2[] = {GPIO47}; > +- > +-static const unsigned pins_ebu_a24[] = {GPIO13}; > +-static const unsigned pins_ebu_clk[] = {GPIO21}; > +-static const unsigned pins_ebu_cs1[] = {GPIO23}; > +-static const unsigned pins_ebu_a23[] = {GPIO24}; > +-static const unsigned pins_ebu_wait[] = {GPIO26}; > +-static const unsigned pins_ebu_a25[] = {GPIO31}; > +-static const unsigned pins_ebu_rdy[] = {GPIO48}; > +-static const unsigned pins_ebu_rd[] = {GPIO49}; > +- > +-static const unsigned pins_nand_ale[] = {GPIO13}; > +-static const unsigned pins_nand_cs1[] = {GPIO23}; > +-static const unsigned pins_nand_cle[] = {GPIO24}; > +-static const unsigned pins_nand_rdy[] = {GPIO48}; > +-static const unsigned pins_nand_rd[] = {GPIO49}; > +- > +-static const unsigned pins_exin0[] = {GPIO0}; > +-static const unsigned pins_exin1[] = {GPIO1}; > +-static const unsigned pins_exin2[] = {GPIO2}; > +-static const unsigned pins_exin3[] = {GPIO39}; > +-static const unsigned pins_exin4[] = {GPIO46}; > +-static const unsigned pins_exin5[] = {GPIO9}; > +- > +-static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18}; > +-static const unsigned pins_spi_cs1[] = {GPIO15}; > +-static const unsigned pins_spi_cs2[] = {GPIO21}; > +-static const unsigned pins_spi_cs3[] = {GPIO13}; > +-static const unsigned pins_spi_cs4[] = {GPIO10}; > +-static const unsigned pins_spi_cs5[] = {GPIO9}; > +-static const unsigned pins_spi_cs6[] = {GPIO11}; > +- > +-static const unsigned pins_gpt1[] = {GPIO28}; > +-static const unsigned pins_gpt2[] = {GPIO21}; > +-static const unsigned pins_gpt3[] = {GPIO6}; > +- > +-static const unsigned pins_clkout0[] = {GPIO8}; > +-static const unsigned pins_clkout1[] = {GPIO7}; > +-static const unsigned pins_clkout2[] = {GPIO3}; > +-static const unsigned pins_clkout3[] = {GPIO2}; > +- > +-static const unsigned pins_pci_gnt1[] = {GPIO30}; > +-static const unsigned pins_pci_gnt2[] = {GPIO23}; > +-static const unsigned pins_pci_gnt3[] = {GPIO19}; > +-static const unsigned pins_pci_gnt4[] = {GPIO38}; > +-static const unsigned pins_pci_req1[] = {GPIO29}; > +-static const unsigned pins_pci_req2[] = {GPIO31}; > +-static const unsigned pins_pci_req3[] = {GPIO3}; > +-static const unsigned pins_pci_req4[] = {GPIO37}; > ++static const unsigned ase_exin_pin_map[] = {GPIO6, GPIO29, GPIO0}; > ++ > ++static const unsigned ase_pins_exin0[] = {GPIO6}; > ++static const unsigned ase_pins_exin1[] = {GPIO29}; > ++static const unsigned ase_pins_exin2[] = {GPIO0}; > + > + static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, > GPIO11}; > + static const unsigned ase_pins_asc[] = {GPIO5, GPIO6}; > + static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3}; > +-static const unsigned ase_pins_ephy[] = {GPIO2, GPIO3, GPIO4}; > +-static const unsigned ase_pins_dfe[] = {GPIO1, GPIO2}; > ++static const unsigned ase_pins_ephy_led0[] = {GPIO2}; > ++static const unsigned ase_pins_ephy_led1[] = {GPIO3}; > ++static const unsigned ase_pins_ephy_led2[] = {GPIO4}; > ++static const unsigned ase_pins_mdio[] = {GPIO24, GPIO27}; > ++static const unsigned ase_pins_dfe_led0[] = {GPIO1}; > ++static const unsigned ase_pins_dfe_led1[] = {GPIO2}; > + > + static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10}; > + static const unsigned ase_pins_spi_cs1[] = {GPIO7}; > + static const unsigned ase_pins_spi_cs2[] = {GPIO15}; > + static const unsigned ase_pins_spi_cs3[] = {GPIO14}; > + > +-static const unsigned ase_pins_exin0[] = {GPIO6}; > +-static const unsigned ase_pins_exin1[] = {GPIO29}; > +-static const unsigned ase_pins_exin2[] = {GPIO0}; > +- > + static const unsigned ase_pins_gpt1[] = {GPIO5}; > + static const unsigned ase_pins_gpt2[] = {GPIO4}; > + static const unsigned ase_pins_gpt3[] = {GPIO25}; > + > +-static const struct ltq_pin_group xway_grps[] = { > +-GRP_MUX("exin0", EXIN, pins_exin0), > +-GRP_MUX("exin1", EXIN, pins_exin1), > +-GRP_MUX("exin2", EXIN, pins_exin2), > +-GRP_MUX("jtag", JTAG, pins_jtag), > +-GRP_MUX("ebu a23", EBU, pins_ebu_a23), > +-GRP_MUX("ebu a24", EBU, pins_ebu_a24), > +-GRP_MUX("ebu a25", EBU, pins_ebu_a25), > +-GRP_MUX("ebu clk", EBU, pins_ebu_clk), > +-GRP_MUX("ebu cs1", EBU, pins_ebu_cs1), > +-GRP_MUX("ebu wait", EBU, pins_ebu_wait), > +-GRP_MUX("nand ale", EBU, pins_nand_ale), > +-GRP_MUX("nand cs1", EBU, pins_nand_cs1), > +-GRP_MUX("nand cle", EBU, pins_nand_cle), > +-GRP_MUX("spi", SPI, pins_spi), > +-GRP_MUX("spi_cs1", SPI, pins_spi_cs1), > +-GRP_MUX("spi_cs2", SPI, pins_spi_cs2), > +-GRP_MUX("spi_cs3", SPI, pins_spi_cs3), > +-GRP_MUX("spi_cs4", SPI, pins_spi_cs4), > +-GRP_MUX("spi_cs5", SPI, pins_spi_cs5), > +-GRP_MUX("spi_cs6", SPI, pins_spi_cs6), > +-GRP_MUX("asc0", ASC, pins_asc0), > +-GRP_MUX("asc0 cts rts", ASC, pins_asc0_cts_rts), > +-GRP_MUX("stp", STP, pins_stp), > +-GRP_MUX("nmi", NMI, pins_nmi), > +-GRP_MUX("gpt1", GPT, pins_gpt1), > +-GRP_MUX("gpt2", GPT, pins_gpt2), > +-GRP_MUX("gpt3", GPT, pins_gpt3), > +-GRP_MUX("clkout0", CGU, pins_clkout0), > +-GRP_MUX("clkout1", CGU, pins_clkout1), > +-GRP_MUX("clkout2", CGU, pins_clkout2), > +-GRP_MUX("clkout3", CGU, pins_clkout3), > +-GRP_MUX("gnt1", PCI, pins_pci_gnt1), > +-GRP_MUX("gnt2", PCI, pins_pci_gnt2), > +-GRP_MUX("gnt3", PCI, pins_pci_gnt3), > +-GRP_MUX("req1", PCI, pins_pci_req1), > +-GRP_MUX("req2", PCI, pins_pci_req2), > +-GRP_MUX("req3", PCI, pins_pci_req3), > +-/* xrx only */ > +-GRP_MUX("nand rdy", EBU, pins_nand_rdy), > +-GRP_MUX("nand rd", EBU, pins_nand_rd), > +-GRP_MUX("exin3", EXIN, pins_exin3), > +-GRP_MUX("exin4", EXIN, pins_exin4), > +-GRP_MUX("exin5", EXIN, pins_exin5), > +-GRP_MUX("gnt4", PCI, pins_pci_gnt4), > +-GRP_MUX("req4", PCI, pins_pci_gnt4), > +-GRP_MUX("mdio", MDIO, pins_mdio), > +-GRP_MUX("gphy0 led0", GPHY, pins_gphy0_led0), > +-GRP_MUX("gphy0 led1", GPHY, pins_gphy0_led1), > +-GRP_MUX("gphy0 led2", GPHY, pins_gphy0_led2), > +-GRP_MUX("gphy1 led0", GPHY, pins_gphy1_led0), > +-GRP_MUX("gphy1 led1", GPHY, pins_gphy1_led1), > +-GRP_MUX("gphy1 led2", GPHY, pins_gphy1_led2), > +-}; > ++static const unsigned ase_pins_clkout0[] = {GPIO23}; > ++static const unsigned ase_pins_clkout1[] = {GPIO22}; > ++static const unsigned ase_pins_clkout2[] = {GPIO14}; > ++ > + > + static const struct ltq_pin_group ase_grps[] = { > + GRP_MUX("exin0", EXIN, ase_pins_exin0), > +@@ -348,101 +188,643 @@ static const struct ltq_pin_group ase_gr > + GRP_MUX("gpt1", GPT, ase_pins_gpt1), > + GRP_MUX("gpt2", GPT, ase_pins_gpt2), > + GRP_MUX("gpt3", GPT, ase_pins_gpt3), > +-GRP_MUX("ephy", EPHY, ase_pins_ephy), > +-GRP_MUX("dfe", DFE, ase_pins_dfe), > ++GRP_MUX("clkout0", CGU, ase_pins_clkout0), > ++GRP_MUX("clkout1", CGU, ase_pins_clkout1), > ++GRP_MUX("clkout2", CGU, ase_pins_clkout2), > ++GRP_MUX("ephy led0", EPHY, ase_pins_ephy_led0), > ++GRP_MUX("ephy led1", EPHY, ase_pins_ephy_led1), > ++GRP_MUX("ephy led2", EPHY, ase_pins_ephy_led2), > ++GRP_MUX("mdio", MDIO, ase_pins_mdio), > ++GRP_MUX("dfe led0", DFE, ase_pins_dfe_led0), > ++GRP_MUX("dfe led1", DFE, ase_pins_dfe_led1), > + GRP_MUX("spi", SPI, ase_pins_spi), > + GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1), > + GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2), > + GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3), > + }; > + > +-static const char * const xway_pci_grps[] = {"gnt1", "gnt2", > ++static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"}; > ++static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; > ++static const char * const ase_cgu_grps[] = {"clkout0", "clkout1", > ++"clkout2"}; > ++static const char * const ase_dfe_grps[] = {"dfe led0", "dfe led1"}; > ++static const char * const ase_ephy_grps[] = {"ephy led0", "ephy led1", > ++"ephy led2"}; > ++static const char * const ase_mdio_grps[] = {"mdio"}; > ++static const char * const ase_asc_grps[] = {"asc"}; > ++static const char * const ase_jtag_grps[] = {"jtag"}; > ++static const char * const ase_stp_grps[] = {"stp"}; > ++static const char * const ase_spi_grps[] = {"spi", "spi_cs1", > ++"spi_cs2", "spi_cs3"}; > ++ > ++static const struct ltq_pmx_func ase_funcs[] = { > ++{"spi",ARRAY_AND_SIZE(ase_spi_grps)}, > ++{"asc",ARRAY_AND_SIZE(ase_asc_grps)}, > ++{"cgu",ARRAY_AND_SIZE(ase_cgu_grps)}, > ++{"jtag",ARRAY_AND_SIZE(ase_jtag_grps)}, > ++{"exin",ARRAY_AND_SIZE(ase_exin_grps)}, > ++{"stp",ARRAY_AND_SIZE(ase_stp_grps)}, > ++{"gpt",ARRAY_AND_SIZE(ase_gpt_grps)}, > ++{"ephy",ARRAY_AND_SIZE(ase_ephy_grps)}, > ++{"mdio",ARRAY_AND_SIZE(ase_mdio_grps)}, > ++{"dfe",ARRAY_AND_SIZE(ase_dfe_grps)}, > ++}; > ++ > ++/* --------- danube related code --------- */ > ++#define DANUBE_MAX_PIN32 > ++ > ++static const struct ltq_mfp_pin danube_mfp[] = { > ++/* pin f0f1f2f3 */ > ++MFP_XWAY(GPIO0, GPIO,EXIN,SDIO,TDM), > ++MFP_XWAY(GPIO1, GPIO,EXIN,CBUS,MII), > ++MFP_XWAY(GPIO2, GPIO,CGU,EXIN,MII), > ++MFP_XWAY(GPIO3, GPIO,CGU,SDIO,PCI), > ++MFP_XWAY(GPIO4, GPIO,STP,DFE,ASC), > ++MFP_XWAY(GPIO5, GPIO,STP,MII,DFE), > ++MFP_XWAY(GPIO6, GPIO,STP,GPT,ASC), > ++MFP_XWAY(GPIO7, GPIO,CGU,CBUS,MII), > ++MFP_XWAY(GPIO8, GPIO,CGU,NMI,MII), > ++MFP_XWAY(GPIO9, GPIO,ASC,SPI,MII), > ++MFP_XWAY(GPIO10, GPIO,ASC,SPI,MII), > ++MFP_XWAY(GPIO11, GPIO,ASC,CBUS,SPI), > ++MFP_XWAY(GPIO12, GPIO,ASC,CBUS,MCD), > ++MFP_XWAY(GPIO13, GPIO,EBU,SPI,MII), > ++MFP_XWAY(GPIO14, GPIO,CGU,CBUS,MII), > ++MFP_XWAY(GPIO15, GPIO,SPI,SDIO,JTAG), > ++MFP_XWAY(GPIO16, GPIO,SPI,SDIO,JTAG), > ++MFP_XWAY(GPIO17, GPIO,SPI,SDIO,JTAG), > ++MFP_XWAY(GPIO18, GPIO,SPI,SDIO,JTAG), > ++MFP_XWAY(GPIO19, GPIO,PCI,SDIO,MII), > ++MFP_XWAY(GPIO20, GPIO,JTAG,SDIO,MII), > ++MFP_XWAY(GPIO21, GPIO,PCI,EBU,GPT), > ++MFP_XWAY(GPIO22, GPIO,SPI,MCD,MII), > ++MFP_XWAY(GPIO23, GPIO,EBU,PCI,STP), > ++MFP_XWAY(GPIO24, GPIO,EBU,TDM,PCI), > ++MFP_XWAY(GPIO25, GPIO,TDM,SDIO,ASC), > ++MFP_XWAY(GPIO26, GPIO,EBU,TDM,SDIO), > ++MFP_XWAY(GPIO27, GPIO,TDM,SDIO,ASC), > ++MFP_XWAY(GPIO28, GPIO,GPT,MII,SDIO), > ++MFP_XWAY(GPIO29, GPIO,PCI,CBUS,MII), > ++MFP_XWAY(GPIO30, GPIO,PCI,CBUS,MII), > ++MFP_XWAY(GPIO31, GPIO,EBU,PCI,MII), > ++}; > ++ > ++static const unsigned danube_exin_pin_map[] = {GPIO0, GPIO1, GPIO2}; > ++ > ++static const unsigned danube_pins_exin0[] = {GPIO0}; > ++static const unsigned danube_pins_exin1[] = {GPIO1}; > ++static const unsigned danube_pins_exin2[] = {GPIO2}; > ++ > ++static const unsigned danube_pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO18, > GPIO20}; > ++static const unsigned danube_pins_asc0[] = {GPIO11, GPIO12}; > ++static const unsigned danube_pins_asc0_cts_rts[] = {GPIO9, GPIO10}; > ++static const unsigned danube_pins_stp[] = {GPIO4, GPIO5, GPIO6}; > ++static const unsigned danube_pins_nmi[] = {GPIO8}; > ++ > ++static const unsigned danube_pins_dfe_led0[] = {GPIO4}; > ++static const unsigned danube_pins_dfe_led1[] = {GPIO5}; > ++ > ++static const unsigned danube_pins_ebu_a24[] = {GPIO13}; > ++static const unsigned danube_pins_ebu_clk[] = {GPIO21}; > ++static const unsigned danube_pins_ebu_cs1[] = {GPIO23}; > ++static const unsigned danube_pins_ebu_a23[] = {GPIO24}; > ++static const unsigned danube_pins_ebu_wait[] = {GPIO26}; > ++static const unsigned danube_pins_ebu_a25[] = {GPIO31}; > ++ > ++static const unsigned danube_pins_nand_ale[] = {GPIO13}; > ++static const unsigned danube_pins_nand_cs1[] = {GPIO23}; > ++static const unsigned danube_pins_nand_cle[] = {GPIO24}; > ++ > ++static const unsigned danube_pins_spi[] = {GPIO16, GPIO17, GPIO18}; > ++static const unsigned danube_pins_spi_cs1[] = {GPIO15}; > ++static const unsigned danube_pins_spi_cs2[] = {GPIO21}; > ++static const unsigned danube_pins_spi_cs3[] = {GPIO13}; > ++static const unsigned danube_pins_spi_cs4[] = {GPIO10}; > ++static const unsigned danube_pins_spi_cs5[] = {GPIO9}; > ++static const unsigned danube_pins_spi_cs6[] = {GPIO11}; > ++ > ++static const unsigned danube_pins_gpt1[] = {GPIO28}; > ++static const unsigned danube_pins_gpt2[] = {GPIO21}; > ++static const unsigned danube_pins_gpt3[] = {GPIO6}; > ++ > ++static const unsigned danube_pins_clkout0[] = {GPIO8}; > ++static const unsigned danube_pins_clkout1[] = {GPIO7}; > ++static const unsigned danube_pins_clkout2[] = {GPIO3}; > ++static const unsigned danube_pins_clkout3[] = {GPIO2}; > ++ > ++static const unsigned danube_pins_pci_gnt1[] = {GPIO30}; > ++static const unsigned danube_pins_pci_gnt2[] = {GPIO23}; > ++static const unsigned danube_pins_pci_gnt3[] = {GPIO19}; > ++static const unsigned danube_pins_pci_req1[] = {GPIO29}; > ++static const unsigned danube_pins_pci_req2[] = {GPIO31}; > ++static const unsigned danube_pins_pci_req3[] = {GPIO3}; > ++ > ++static const struct ltq_pin_group danube_grps[] = { > ++GRP_MUX("exin0", EXIN, danube_pins_exin0), > ++GRP_MUX("exin1", EXIN, danube_pins_exin1), > ++GRP_MUX("exin2", EXIN, danube_pins_exin2), > ++GRP_MUX("jtag", JTAG, danube_pins_jtag), > ++GRP_MUX("dfe led0", DFE, danube_pins_dfe_led0), > ++GRP_MUX("dfe led1", DFE, danube_pins_dfe_led1), > ++GRP_MUX("ebu a23", EBU, danube_pins_ebu_a23), > ++GRP_MUX("ebu a24", EBU, danube_pins_ebu_a24), > ++GRP_MUX("ebu a25", EBU, danube_pins_ebu_a25), > ++GRP_MUX("ebu clk", EBU, danube_pins_ebu_clk), > ++GRP_MUX("ebu cs1", EBU, danube_pins_ebu_cs1), > ++GRP_MUX("ebu wait", EBU, danube_pins_ebu_wait), > ++GRP_MUX("nand ale", EBU, danube_pins_nand_ale), > ++GRP_MUX("nand cs1", EBU, danube_pins_nand_cs1), > ++GRP_MUX("nand cle", EBU, danube_pins_nand_cle), > ++GRP_MUX("spi", SPI, danube_pins_spi), > ++GRP_MUX("spi_cs1", SPI, danube_pins_spi_cs1), > ++GRP_MUX("spi_cs2", SPI, danube_pins_spi_cs2), > ++GRP_MUX("spi_cs3", SPI, danube_pins_spi_cs3), > ++GRP_MUX("spi_cs4", SPI, danube_pins_spi_cs4), > ++GRP_MUX("spi_cs5", SPI, danube_pins_spi_cs5), > ++GRP_MUX("spi_cs6", SPI, danube_pins_spi_cs6), > ++GRP_MUX("asc0", ASC, danube_pins_asc0), > ++GRP_MUX("asc0 cts rts", ASC, danube_pins_asc0_cts_rts), > ++GRP_MUX("stp", STP, danube_pins_stp), > ++GRP_MUX("nmi", NMI, danube_pins_nmi), > ++GRP_MUX("gpt1", GPT, danube_pins_gpt1), > ++GRP_MUX("gpt2", GPT, danube_pins_gpt2), > ++GRP_MUX("gpt3", GPT, danube_pins_gpt3), > ++GRP_MUX("clkout0", CGU, danube_pins_clkout0), > ++GRP_MUX("clkout1", CGU, danube_pins_clkout1), > ++GRP_MUX("clkout2", CGU, danube_pins_clkout2), > ++GRP_MUX("clkout3", CGU, danube_pins_clkout3), > ++GRP_MUX("gnt1", PCI, danube_pins_pci_gnt1), > ++GRP_MUX("gnt2", PCI, danube_pins_pci_gnt2), > ++GRP_MUX("gnt3", PCI, danube_pins_pci_gnt3), > ++GRP_MUX("req1", PCI, danube_pins_pci_req1), > ++GRP_MUX("req2", PCI, danube_pins_pci_req2), > ++GRP_MUX("req3", PCI, danube_pins_pci_req3), > ++}; > ++ > ++static const char * const danube_pci_grps[] = {"gnt1", "gnt2", > + "gnt3", "req1", > + "req2", "req3"}; > +-static const char * const xway_spi_grps[] = {"spi", "spi_cs1", > ++static const char * const danube_spi_grps[] = {"spi", "spi_cs1", > + "spi_cs2", "spi_cs3", > + "spi_cs4", "spi_cs5", > + "spi_cs6"}; > +-static const char * const xway_cgu_grps[] = {"clkout0", "clkout1", > ++static const char * const danube_cgu_grps[] = {"clkout0", "clkout1", > + "clkout2", "clkout3"}; > +-static const char * const xway_ebu_grps[] = {"ebu a23", "ebu a24", > ++static const char * const danube_ebu_grps[] = {"ebu a23", "ebu a24", > + "ebu a25", "ebu cs1", > + "ebu wait", "ebu clk", > + "nand ale", "nand cs1", > + "nand cle"}; > +-static const char * const xway_exin_grps[] = {"exin0", "exin1", "exin2"}; > +-static const char * const xway_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; > +-static const char * const xway_asc_grps[] = {"asc0", "asc0 cts rts"}; > +-static const char * const xway_jtag_grps[] = {"jtag"}; > +-static const char * const xway_stp_grps[] = {"stp"}; > +-static const char * const xway_nmi_grps[] = {"nmi"}; > +- > +-/* ar9/vr9/gr9 */ > +-static const char * const xrx_mdio_grps[] = {"mdio"}; > +-static const char * const xrx_gphy_grps[] = {"gphy0 led0", "gphy0 led1", > +-"gphy0 led2", "gphy1 led0", > +-"gphy1 led1", "gphy1 led2"}; > +-static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24", > ++static const char * const danube_dfe_grps[] = {"dfe led0", "dfe led1"}; > ++static const char * const danube_exin_grps[] = {"exin0", "exin1", "exin2"}; > ++static const char * const danube_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; > ++static const char * const danube_asc_grps[] = {"asc0", "asc0 cts rts"}; > ++static const char * const danube_jtag_grps[] = {"jtag"}; > ++static const char * const danube_stp_grps[] = {"stp"}; > ++static const char * const danube_nmi_grps[] = {"nmi"}; > ++ > ++static const struct ltq_pmx_func danube_funcs[] = { > ++{"spi",ARRAY_AND_SIZE(danube_spi_grps)}, > ++{"asc",ARRAY_AND_SIZE(danube_asc_grps)}, > ++{"cgu",ARRAY_AND_SIZE(danube_cgu_grps)}, > ++{"jtag",ARRAY_AND_SIZE(danube_jtag_grps)}, > ++{"exin",ARRAY_AND_SIZE(danube_exin_grps)}, > ++{"stp",ARRAY_AND_SIZE(danube_stp_grps)}, > ++{"gpt",ARRAY_AND_SIZE(danube_gpt_grps)}, > ++{"nmi",ARRAY_AND_SIZE(danube_nmi_grps)}, > ++{"pci",ARRAY_AND_SIZE(danube_pci_grps)}, > ++{"ebu",ARRAY_AND_SIZE(danube_ebu_grps)}, > ++{"dfe",ARRAY_AND_SIZE(danube_dfe_grps)}, > ++}; > ++ > ++/* --------- xrx100 related code --------- */ > ++#define XRX100_MAX_PIN56 > ++ > ++static const struct ltq_mfp_pin xrx100_mfp[] = { > ++/* pin f0f1f2f3 */ > ++MFP_XWAY(GPIO0, GPIO,EXIN,SDIO,TDM), > ++MFP_XWAY(GPIO1, GPIO,EXIN,CBUS,SIN), > ++MFP_XWAY(GPIO2, GPIO,CGU,EXIN,NONE), > ++MFP_XWAY(GPIO3, GPIO,CGU,SDIO,PCI), > ++MFP_XWAY(GPIO4, GPIO,STP,DFE,ASC), > ++MFP_XWAY(GPIO5, GPIO,STP,NONE,DFE), > ++MFP_XWAY(GPIO6, GPIO,STP,GPT,ASC), > ++MFP_XWAY(GPIO7, GPIO,CGU,CBUS,NONE), > ++MFP_XWAY(GPIO8, GPIO,CGU,NMI,NONE), > ++MFP_XWAY(GPIO9, GPIO,ASC,SPI,EXIN), > ++MFP_XWAY(GPIO10, GPIO,ASC,SPI,EXIN), > ++MFP_XWAY(GPIO11, GPIO,ASC,CBUS,SPI), > ++MFP_XWAY(GPIO12, GPIO,ASC,CBUS,MCD), > ++MFP_XWAY(GPIO13, GPIO,EBU,SPI,NONE), > ++MFP_XWAY(GPIO14, GPIO,CGU,NONE,NONE), > ++MFP_XWAY(GPIO15, GPIO,SPI,SDIO,MCD), > ++MFP_XWAY(GPIO16, GPIO,SPI,SDIO,NONE), > ++MFP_XWAY(GPIO17, GPIO,SPI,SDIO,NONE), > ++MFP_XWAY(GPIO18, GPIO,SPI,SDIO,NONE), > ++MFP_XWAY(GPIO19, GPIO,PCI,SDIO,CGU), > ++MFP_XWAY(GPIO20, GPIO,NONE,SDIO,EBU), > ++MFP_XWAY(GPIO21, GPIO,PCI,EBU,GPT), > ++MFP_XWAY(GPIO22, GPIO,SPI,NONE,EBU), > ++MFP_XWAY(GPIO23, GPIO,EBU,PCI,STP), > ++MFP_XWAY(GPIO24, GPIO,EBU,TDM,PCI), > ++MFP_XWAY(GPIO25, GPIO,TDM,SDIO,ASC), > ++MFP_XWAY(GPIO26, GPIO,EBU,TDM,SDIO), > ++MFP_XWAY(GPIO27, GPIO,TDM,SDIO,ASC), > ++MFP_XWAY(GPIO28, GPIO,GPT,NONE,SDIO), > ++MFP_XWAY(GPIO29, GPIO,PCI,CBUS,NONE), > ++MFP_XWAY(GPIO30, GPIO,PCI,CBUS,NONE), > ++MFP_XWAY(GPIO31, GPIO,EBU,PCI,NONE), > ++MFP_XWAY(GPIO32, GPIO,MII,NONE,EBU), > ++MFP_XWAY(GPIO33, GPIO,MII,NONE,EBU), > ++MFP_XWAY(GPIO34, GPIO,SIN,SSI,NONE), > ++MFP_XWAY(GPIO35, GPIO,SIN,SSI,NONE), > ++MFP_XWAY(GPIO36, GPIO,SIN,SSI,NONE), > ++MFP_XWAY(GPIO37, GPIO,PCI,NONE,NONE), > ++MFP_XWAY(GPIO38, GPIO,PCI,NONE,NONE), > ++MFP_XWAY(GPIO39, GPIO,NONE,EXIN,NONE), > ++MFP_XWAY(GPIO40, GPIO,MII,TDM,NONE), > ++MFP_XWAY(GPIO41, GPIO,MII,TDM,NONE), > ++MFP_XWAY(GPIO42, GPIO,MDIO,NONE,NONE), > ++MFP_XWAY(GPIO43, GPIO,MDIO,NONE,NONE), > ++MFP_XWAY(GPIO44, GPIO,MII,SIN,NONE), > ++MFP_XWAY(GPIO45, GPIO,MII,NONE,SIN), > ++MFP_XWAY(GPIO46, GPIO,MII,NONE,EXIN), > ++MFP_XWAY(GPIO47, GPIO,MII,NONE,SIN), > ++MFP_XWAY(GPIO48, GPIO,EBU,NONE,NONE), > ++MFP_XWAY(GPIO49, GPIO,EBU,NONE,NONE), > ++MFP_XWAY(GPIO50, GPIO,NONE,NONE,NONE), > ++MFP_XWAY(GPIO51, GPIO,NONE,NONE,NONE), > ++MFP_XWAY(GPIO52, GPIO,NONE,NONE,NONE), > ++MFP_XWAY(GPIO53, GPIO,NONE,NONE,NONE), > ++MFP_XWAY(GPIO54, GPIO,NONE,NONE,NONE), > ++MFP_XWAY(GPIO55, GPIO,NONE,NONE,NONE), > ++}; > ++ > ++static const unsigned xrx100_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, > GPIO10, GPIO9}; > ++ > ++static const unsigned xrx100_pins_exin0[] = {GPIO0}; > ++static const unsigned xrx100_pins_exin1[] = {GPIO1}; > ++static const unsigned xrx100_pins_exin2[] = {GPIO2}; > ++static const unsigned xrx100_pins_exin3[] = {GPIO39}; > ++static const unsigned xrx100_pins_exin4[] = {GPIO10}; > ++static const unsigned xrx100_pins_exin5[] = {GPIO9}; > ++ > ++static const unsigned xrx100_pins_asc0[] = {GPIO11, GPIO12}; > ++static const unsigned xrx100_pins_asc0_cts_rts[] = {GPIO9, GPIO10}; > ++static const unsigned xrx100_pins_stp[] = {GPIO4, GPIO5, GPIO6}; > ++static const unsigned xrx100_pins_nmi[] = {GPIO8}; > ++static const unsigned xrx100_pins_mdio[] = {GPIO42, GPIO43}; > ++ > ++static const unsigned xrx100_pins_ebu_a24[] = {GPIO13}; > ++static const unsigned xrx100_pins_ebu_clk[] = {GPIO21}; > ++static const unsigned xrx100_pins_ebu_cs1[] = {GPIO23}; > ++static const unsigned xrx100_pins_ebu_a23[] = {GPIO24}; > ++static const unsigned xrx100_pins_ebu_wait[] = {GPIO26}; > ++static const unsigned xrx100_pins_ebu_a25[] = {GPIO31}; > ++ > ++static const unsigned xrx100_pins_nand_ale[] = {GPIO13}; > ++static const unsigned xrx100_pins_nand_cs1[] = {GPIO23}; > ++static const unsigned xrx100_pins_nand_cle[] = {GPIO24}; > ++static const unsigned xrx100_pins_nand_rdy[] = {GPIO48}; > ++static const unsigned xrx100_pins_nand_rd[] = {GPIO49}; > ++ > ++static const unsigned xrx100_pins_spi[] = {GPIO16, GPIO17, GPIO18}; > ++static const unsigned xrx100_pins_spi_cs1[] = {GPIO15}; > ++static const unsigned xrx100_pins_spi_cs2[] = {GPIO22}; > ++static const unsigned xrx100_pins_spi_cs3[] = {GPIO13}; > ++static const unsigned xrx100_pins_spi_cs4[] = {GPIO10}; > ++static const unsigned xrx100_pins_spi_cs5[] = {GPIO9}; > ++static const unsigned xrx100_pins_spi_cs6[] = {GPIO11}; > ++ > ++static const unsigned xrx100_pins_gpt1[] = {GPIO28}; > ++static const unsigned xrx100_pins_gpt2[] = {GPIO21}; > ++static const unsigned xrx100_pins_gpt3[] = {GPIO6}; > ++ > ++static const unsigned xrx100_pins_clkout0[] = {GPIO8}; > ++static const unsigned xrx100_pins_clkout1[] = {GPIO7}; > ++static const unsigned xrx100_pins_clkout2[] = {GPIO3}; > ++static const unsigned xrx100_pins_clkout3[] = {GPIO2}; > ++ > ++static const unsigned xrx100_pins_pci_gnt1[] = {GPIO30}; > ++static const unsigned xrx100_pins_pci_gnt2[] = {GPIO23}; > ++static const unsigned xrx100_pins_pci_gnt3[] = {GPIO19}; > ++static const unsigned xrx100_pins_pci_req1[] = {GPIO29}; > ++static const unsigned xrx100_pins_pci_req2[] = {GPIO31}; > ++static const unsigned xrx100_pins_pci_req3[] = {GPIO3}; > ++ > ++static const struct ltq_pin_group xrx100_grps[] = { > ++GRP_MUX("exin0", EXIN, xrx100_pins_exin0), > ++GRP_MUX("exin1", EXIN, xrx100_pins_exin1), > ++GRP_MUX("exin2", EXIN, xrx100_pins_exin2), > ++GRP_MUX("exin3", EXIN, xrx100_pins_exin3), > ++GRP_MUX("exin4", EXIN, xrx100_pins_exin4), > ++GRP_MUX("exin5", EXIN, xrx100_pins_exin5), > ++GRP_MUX("ebu a23", EBU, xrx100_pins_ebu_a23), > ++GRP_MUX("ebu a24", EBU, xrx100_pins_ebu_a24), > ++GRP_MUX("ebu a25", EBU, xrx100_pins_ebu_a25), > ++GRP_MUX("ebu clk", EBU, xrx100_pins_ebu_clk), > ++GRP_MUX("ebu cs1", EBU, xrx100_pins_ebu_cs1), > ++GRP_MUX("ebu wait", EBU, xrx100_pins_ebu_wait), > ++GRP_MUX("nand ale", EBU, xrx100_pins_nand_ale), > ++GRP_MUX("nand cs1", EBU, xrx100_pins_nand_cs1), > ++GRP_MUX("nand cle", EBU, xrx100_pins_nand_cle), > ++GRP_MUX("nand rdy", EBU, xrx100_pins_nand_rdy), > ++GRP_MUX("nand rd", EBU, xrx100_pins_nand_rd), > ++GRP_MUX("spi", SPI, xrx100_pins_spi), > ++GRP_MUX("spi_cs1", SPI, xrx100_pins_spi_cs1), > ++GRP_MUX("spi_cs2", SPI, xrx100_pins_spi_cs2), > ++GRP_MUX("spi_cs3", SPI, xrx100_pins_spi_cs3), > ++GRP_MUX("spi_cs4", SPI, xrx100_pins_spi_cs4), > ++GRP_MUX("spi_cs5", SPI, xrx100_pins_spi_cs5), > ++GRP_MUX("spi_cs6", SPI, xrx100_pins_spi_cs6), > ++GRP_MUX("asc0", ASC, xrx100_pins_asc0), > ++GRP_MUX("asc0 cts rts", ASC, xrx100_pins_asc0_cts_rts), > ++GRP_MUX("stp", STP, xrx100_pins_stp), > ++GRP_MUX("nmi", NMI, xrx100_pins_nmi), > ++GRP_MUX("gpt1", GPT, xrx100_pins_gpt1), > ++GRP_MUX("gpt2", GPT, xrx100_pins_gpt2), > ++GRP_MUX("gpt3", GPT, xrx100_pins_gpt3), > ++GRP_MUX("clkout0", CGU, xrx100_pins_clkout0), > ++GRP_MUX("clkout1", CGU, xrx100_pins_clkout1), > ++GRP_MUX("clkout2", CGU, xrx100_pins_clkout2), > ++GRP_MUX("clkout3", CGU, xrx100_pins_clkout3), > ++GRP_MUX("gnt1", PCI, xrx100_pins_pci_gnt1), > ++GRP_MUX("gnt2", PCI, xrx100_pins_pci_gnt2), > ++GRP_MUX("gnt3", PCI, xrx100_pins_pci_gnt3), > ++GRP_MUX("req1", PCI, xrx100_pins_pci_req1), > ++GRP_MUX("req2", PCI, xrx100_pins_pci_req2), > ++GRP_MUX("req3", PCI, xrx100_pins_pci_req3), > ++GRP_MUX("mdio", MDIO, xrx100_pins_mdio), > ++}; > ++ > ++static const char * const xrx100_pci_grps[] = {"gnt1", "gnt2", > ++"gnt3", "req1", > ++"req2", "req3"}; > ++static const char * const xrx100_spi_grps[] = {"spi", "spi_cs1", > ++"spi_cs2", "spi_cs3", > ++"spi_cs4", "spi_cs5", > ++"spi_cs6"}; > ++static const char * const xrx100_cgu_grps[] = {"clkout0", "clkout1", > ++"clkout2", "clkout3"}; > ++static const char * const xrx100_ebu_grps[] = {"ebu a23", "ebu a24", > + "ebu a25", "ebu cs1", > + "ebu wait", "ebu clk", > + "nand ale", "nand cs1", > + "nand cle", "nand rdy", > + "nand rd"}; > +-static const char * const xrx_exin_grps[] = {"exin0", "exin1", "exin2", > ++static const char * const xrx100_exin_grps[] = {"exin0", "exin1", "exin2", > + "exin3", "exin4", "exin5"}; > +-static const char * const xrx_pci_grps[] = {"gnt1", "gnt2", > +-"gnt3", "gnt4", > +-"req1", "req2", > +-"req3", "req4"}; > ++static const char * const xrx100_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; > ++static const char * const xrx100_asc_grps[] = {"asc0", "asc0 cts rts"}; > ++static const char * const xrx100_stp_grps[] = {"stp"}; > ++static const char * const xrx100_nmi_grps[] = {"nmi"}; > ++static const char * const xrx100_mdio_grps[] = {"mdio"}; > ++ > ++static const struct ltq_pmx_func xrx100_funcs[] = { > ++{"spi",ARRAY_AND_SIZE(xrx100_spi_grps)}, > ++{"asc",ARRAY_AND_SIZE(xrx100_asc_grps)}, > ++{"cgu",ARRAY_AND_SIZE(xrx100_cgu_grps)}, > ++{"exin",ARRAY_AND_SIZE(xrx100_exin_grps)}, > ++{"stp",ARRAY_AND_SIZE(xrx100_stp_grps)}, > ++{"gpt",ARRAY_AND_SIZE(xrx100_gpt_grps)}, > ++{"nmi",ARRAY_AND_SIZE(xrx100_nmi_grps)}, > ++{"pci",ARRAY_AND_SIZE(xrx100_pci_grps)}, > ++{"ebu",ARRAY_AND_SIZE(xrx100_ebu_grps)}, > ++{"mdio",ARRAY_AND_SIZE(xrx100_mdio_grps)}, > ++}; > + > +-/* ase */ > +-static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"}; > +-static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; > +-static const char * const ase_dfe_grps[] = {"dfe"}; > +-static const char * const ase_ephy_grps[] = {"ephy"}; > +-static const char * const ase_asc_grps[] = {"asc"}; > +-static const char * const ase_jtag_grps[] = {"jtag"}; > +-static const char * const ase_stp_grps[] = {"stp"}; > +-static const char * const ase_spi_grps[] = {"spi", "spi_cs1", > +-"spi_cs2", "spi_cs3"}; > ++/* --------- xrx200 related code --------- */ > ++#define XRX200_MAX_PIN50 > + > +-static const struct ltq_pmx_func danube_funcs[] = { > +-{"spi",ARRAY_AND_SIZE(xway_spi_grps)}, > +-{"asc",ARRAY_AND_SIZE(xway_asc_grps)}, > +-{"cgu",ARRAY_AND_SIZE(xway_cgu_grps)}, > +-{"jtag",ARRAY_AND_SIZE(xway_jtag_grps)}, > +-{"exin",ARRAY_AND_SIZE(xway_exin_grps)}, > +-{"stp",ARRAY_AND_SIZE(xway_stp_grps)}, > +-{"gpt",ARRAY_AND_SIZE(xway_gpt_grps)}, > +-{"nmi",ARRAY_AND_SIZE(xway_nmi_grps)}, > +-{"pci",ARRAY_AND_SIZE(xway_pci_grps)}, > +-{"ebu",ARRAY_AND_SIZE(xway_ebu_grps)}, > +-}; > +- > +-static const struct ltq_pmx_func xrx_funcs[] = { > +-{"spi",ARRAY_AND_SIZE(xway_spi_grps)}, > +-{"asc",ARRAY_AND_SIZE(xway_asc_grps)}, > +-{"cgu",ARRAY_AND_SIZE(xway_cgu_grps)}, > +-{"jtag",ARRAY_AND_SIZE(xway_jtag_grps)}, > +-{"exin",ARRAY_AND_SIZE(xrx_exin_grps)}, > +-{"stp",ARRAY_AND_SIZE(xway_stp_grps)}, > +-{"gpt",ARRAY_AND_SIZE(xway_gpt_grps)}, > +-{"nmi",ARRAY_AND_SIZE(xway_nmi_grps)}, > +-{"pci",ARRAY_AND_SIZE(xrx_pci_grps)}, > +-{"ebu",ARRAY_AND_SIZE(xrx_ebu_grps)}, > +-{"mdio",ARRAY_AND_SIZE(xrx_mdio_grps)}, > +-{"gphy",ARRAY_AND_SIZE(xrx_gphy_grps)}, > ++static const struct ltq_mfp_pin xrx200_mfp[] = { > ++/* pin f0f1f2f3 */ > ++MFP_XWAY(GPIO0, GPIO,EXIN,SDIO,TDM), > ++MFP_XWAY(GPIO1, GPIO,EXIN,CBUS,SIN), > ++MFP_XWAY(GPIO2, GPIO,CGU,EXIN,GPHY), > ++MFP_XWAY(GPIO3, GPIO,CGU,SDIO,PCI), > ++MFP_XWAY(GPIO4, GPIO,STP,DFE,USIF), > ++MFP_XWAY(GPIO5, GPIO,STP,GPHY,DFE), > ++MFP_XWAY(GPIO6, GPIO,STP,GPT,USIF), > ++MFP_XWAY(GPIO7, GPIO,CGU,CBUS,GPHY), > ++MFP_XWAY(GPIO8, GPIO,CGU,NMI,NONE), > ++MFP_XWAY(GPIO9, GPIO,USIF,SPI,EXIN), > ++MFP_XWAY(GPIO10, GPIO,USIF,SPI,EXIN), > ++MFP_XWAY(GPIO11, GPIO,USIF,CBUS,SPI), > ++MFP_XWAY(GPIO12, GPIO,USIF,CBUS,MCD), > ++MFP_XWAY(GPIO13, GPIO,EBU,SPI,NONE), > ++MFP_XWAY(GPIO14, GPIO,CGU,CBUS,USIF), > ++MFP_XWAY(GPIO15, GPIO,SPI,SDIO,MCD), > ++MFP_XWAY(GPIO16, GPIO,SPI,SDIO,NONE), > ++MFP_XWAY(GPIO17, GPIO,SPI,SDIO,NONE), > ++MFP_XWAY(GPIO18, GPIO,SPI,SDIO,NONE), > ++MFP_XWAY(GPIO19, GPIO,PCI,SDIO,CGU), > ++MFP_XWAY(GPIO20, GPIO,NONE,SDIO,EBU), > ++MFP_XWAY(GPIO21, GPIO,PCI,EBU,GPT), > ++MFP_XWAY(GPIO22, GPIO,SPI,CGU,EBU), > ++MFP_XWAY(GPIO23, GPIO,EBU,PCI,STP), > ++MFP_XWAY(GPIO24, GPIO,EBU,TDM,PCI), > ++MFP_XWAY(GPIO25, GPIO,TDM,SDIO,USIF), > ++MFP_XWAY(GPIO26, GPIO,EBU,TDM,SDIO), > ++MFP_XWAY(GPIO27, GPIO,TDM,SDIO,USIF), > ++MFP_XWAY(GPIO28, GPIO,GPT,PCI,SDIO), > ++MFP_XWAY(GPIO29, GPIO,PCI,CBUS,EXIN), > ++MFP_XWAY(GPIO30, GPIO,PCI,CBUS,NONE), > ++MFP_XWAY(GPIO31, GPIO,EBU,PCI,NONE), > ++MFP_XWAY(GPIO32, GPIO,MII,NONE,EBU), > ++MFP_XWAY(GPIO33, GPIO,MII,NONE,EBU), > ++MFP_XWAY(GPIO34, GPIO,SIN,SSI,NONE), > ++MFP_XWAY(GPIO35, GPIO,SIN,SSI,NONE), > ++MFP_XWAY(GPIO36, GPIO,SIN,SSI,EXIN), > ++MFP_XWAY(GPIO37, GPIO,USIF,NONE,PCI), > ++MFP_XWAY(GPIO38, GPIO,PCI,USIF,NONE), > ++MFP_XWAY(GPIO39, GPIO,USIF,EXIN,NONE), > ++MFP_XWAY(GPIO40, GPIO,MII,TDM,NONE), > ++MFP_XWAY(GPIO41, GPIO,MII,TDM,NONE), > ++MFP_XWAY(GPIO42, GPIO,MDIO,NONE,NONE), > ++MFP_XWAY(GPIO43, GPIO,MDIO,NONE,NONE), > ++MFP_XWAY(GPIO44, GPIO,MII,SIN,GPHY), > ++MFP_XWAY(GPIO45, GPIO,MII,GPHY,SIN), > ++MFP_XWAY(GPIO46, GPIO,MII,NONE,EXIN), > +MFP_XWAY(GPIO47, GPIO,MII,GPHY,SIN), > - MFP_XWAY(GPIO48, GPIO,EBU,NONE,NONE), > - MFP_XWAY(GPIO49, GPIO,EBU,NONE,NONE), > - MFP_XWAY(GPIO50, GPIO,NONE,NONE,NONE), > ++MFP_XWAY(GPIO48, GPIO,EBU,NONE,NONE), > ++MFP_XWAY(GPIO49, GPIO,EBU,NONE,NONE), > + }; > + > +-static const struct ltq_pmx_func ase_funcs[] = { > +-{"spi",ARRAY_AND_SIZE(ase_spi_grps)}, > +-{"asc",ARRAY_AND_SIZE(ase_asc_grps)}, > +-{"jtag",ARRAY_AND_SIZE(ase_jtag_grps)}, > +-{"exin",ARRAY_AND_SIZE(ase_exin_grps)}, > +-{"stp",ARRAY_AND_SIZE(ase_stp_grps)}, > +-{"gpt",ARRAY_AND_SIZE(ase_gpt_grps)}, > +-{"ephy",ARRAY_AND_SIZE(ase_ephy_grps)}, > +-{"dfe",ARRAY_AND_SIZE(ase_dfe_grps)}, > ++static const unsigned xrx200_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, > GPIO10, GPIO9}; > ++ > ++static const unsigned xrx200_pins_exin0[] = {GPIO0}; > ++static const unsigned xrx200_pins_exin1[] = {GPIO1}; > ++static const unsigned xrx200_pins_exin2[] = {GPIO2}; > ++static const unsigned xrx200_pins_exin3[] = {GPIO39}; > ++static const unsigned xrx200_pins_exin4[] = {GPIO10}; > ++static const unsigned xrx200_pins_exin5[] = {GPIO9}; > ++ > ++static const unsigned xrx200_pins_usif_uart[] = {GPIO11, GPIO12}; > ++static const unsigned xrx200_pins_usif_uart_rts_cts[] = {GPIO9, GPIO10}; > ++static const unsigned xrx200_pins_usif_uart_dtr_dsr[] = {GPIO4, GPIO6}; > ++static const unsigned xrx200_pins_usif_uart_dcd[] = {GPIO25}; > ++static const unsigned xrx200_pins_usif_uart_ri[] = {GPIO27}; > ++ > ++static const unsigned xrx200_pins_usif_spi[] = {GPIO11, GPIO12, GPIO38}; > ++static const unsigned xrx200_pins_usif_spi_cs0[] = {GPIO37}; > ++static const unsigned xrx200_pins_usif_spi_cs1[] = {GPIO39}; > ++static const unsigned xrx200_pins_usif_spi_cs2[] = {GPIO14}; > ++ > ++static const unsigned xrx200_pins_stp[] = {GPIO4, GPIO5, GPIO6}; > ++static const unsigned xrx200_pins_nmi[] = {GPIO8}; > ++static const unsigned xrx200_pins_mdio[] = {GPIO42, GPIO43}; > ++ > ++static const unsigned xrx200_pins_dfe_led0[] = {GPIO4}; > ++static const unsigned xrx200_pins_dfe_led1[] = {GPIO5}; > ++ > ++static const unsigned xrx200_pins_gphy0_led0[] = {GPIO5}; > ++static const unsigned xrx200_pins_gphy0_led1[] = {GPIO7}; > ++static const unsigned xrx200_pins_gphy0_led2[] = {GPIO2}; > ++static const unsigned xrx200_pins_gphy1_led0[] = {GPIO44}; > ++static const unsigned xrx200_pins_gphy1_led1[] = {GPIO45}; > ++static const unsigned xrx200_pins_gphy1_led2[] = {GPIO47}; > ++ > ++static const unsigned xrx200_pins_ebu_a24[] = {GPIO13}; > ++static const unsigned xrx200_pins_ebu_clk[] = {GPIO21}; > ++static const unsigned xrx200_pins_ebu_cs1[] = {GPIO23}; > ++static const unsigned xrx200_pins_ebu_a23[] = {GPIO24}; > ++static const unsigned xrx200_pins_ebu_wait[] = {GPIO26}; > ++static const unsigned xrx200_pins_ebu_a25[] = {GPIO31}; > ++ > ++static const unsigned xrx200_pins_nand_ale[] = {GPIO13}; > ++static const unsigned xrx200_pins_nand_cs1[] = {GPIO23}; > ++static const unsigned xrx200_pins_nand_cle[] = {GPIO24}; > ++static const unsigned xrx200_pins_nand_rdy[] = {GPIO48}; > ++static const unsigned xrx200_pins_nand_rd[] = {GPIO49}; > ++ > ++static const unsigned xrx200_pins_spi[] = {GPIO16, GPIO17, GPIO18}; > ++static const unsigned xrx200_pins_spi_cs1[] = {GPIO15}; > ++static const unsigned xrx200_pins_spi_cs2[] = {GPIO22}; > ++static const unsigned xrx200_pins_spi_cs3[] = {GPIO13}; > ++static const unsigned xrx200_pins_spi_cs4[] = {GPIO10}; > ++static const unsigned xrx200_pins_spi_cs5[] = {GPIO9}; > ++static const unsigned xrx200_pins_spi_cs6[] = {GPIO11}; > ++ > ++static const unsigned xrx200_pins_gpt1[] = {GPIO28}; > ++static const unsigned xrx200_pins_gpt2[] = {GPIO21}; > ++static const unsigned xrx200_pins_gpt3[] = {GPIO6}; > ++ > ++static const unsigned xrx200_pins_clkout0[] = {GPIO8}; > ++static const unsigned xrx200_pins_clkout1[] = {GPIO7}; > ++static const unsigned xrx200_pins_clkout2[] = {GPIO3}; > ++static const unsigned xrx200_pins_clkout3[] = {GPIO2}; > ++ > ++static const unsigned xrx200_pins_pci_gnt1[] = {GPIO28}; > ++static const unsigned xrx200_pins_pci_gnt2[] = {GPIO23}; > ++static const unsigned xrx200_pins_pci_gnt3[] = {GPIO19}; > ++static const unsigned xrx200_pins_pci_req1[] = {GPIO29}; > ++static const unsigned xrx200_pins_pci_req2[] = {GPIO31}; > ++static const unsigned xrx200_pins_pci_req3[] = {GPIO3}; > ++ > ++static const struct ltq_pin_group xrx200_grps[] = { > ++GRP_MUX("exin0", EXIN, xrx200_pins_exin0), > ++GRP_MUX("exin1", EXIN, xrx200_pins_exin1), > ++GRP_MUX("exin2", EXIN, xrx200_pins_exin2), > ++GRP_MUX("exin3", EXIN, xrx200_pins_exin3), > ++GRP_MUX("exin4", EXIN, xrx200_pins_exin4), > ++GRP_MUX("exin5", EXIN, xrx200_pins_exin5), > ++GRP_MUX("ebu a23", EBU, xrx200_pins_ebu_a23), > ++GRP_MUX("ebu a24", EBU, xrx200_pins_ebu_a24), > ++GRP_MUX("ebu a25", EBU, xrx200_pins_ebu_a25), > ++GRP_MUX("ebu clk", EBU, xrx200_pins_ebu_clk), > ++GRP_MUX("ebu cs1", EBU, xrx200_pins_ebu_cs1), > ++GRP_MUX("ebu wait", EBU, xrx200_pins_ebu_wait), > ++GRP_MUX("nand ale", EBU, xrx200_pins_nand_ale), > ++GRP_MUX("nand cs1", EBU, xrx200_pins_nand_cs1), > ++GRP_MUX("nand cle", EBU, xrx200_pins_nand_cle), > ++GRP_MUX("nand rdy", EBU, xrx200_pins_nand_rdy), > ++GRP_MUX("nand rd", EBU, xrx200_pins_nand_rd), > ++GRP_MUX("spi", SPI, xrx200_pins_spi), > ++GRP_MUX("spi_cs1", SPI, xrx200_pins_spi_cs1), > ++GRP_MUX("spi_cs2", SPI, xrx200_pins_spi_cs2), > ++GRP_MUX("spi_cs3", SPI, xrx200_pins_spi_cs3), > ++GRP_MUX("spi_cs4", SPI, xrx200_pins_spi_cs4), > ++GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5), > ++GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6), > ++GRP_MUX("usif uart", USIF, xrx200_pins_usif_uart), > ++GRP_MUX("usif uart_rts_cts", USIF, xrx200_pins_usif_uart_rts_cts), > ++GRP_MUX("usif uart_dtr_dsr", USIF, xrx200_pins_usif_uart_dtr_dsr), > ++GRP_MUX("usif uart_dcd", USIF, xrx200_pins_usif_uart_dcd), > ++GRP_MUX("usif uart_ri", USIF, xrx200_pins_usif_uart_ri), > ++GRP_MUX("usif spi", USIF, xrx200_pins_usif_spi), > ++GRP_MUX("usif spi_cs0", USIF, xrx200_pins_usif_spi_cs0), > ++GRP_MUX("usif spi_cs1", USIF, xrx200_pins_usif_spi_cs1), > ++GRP_MUX("usif spi_cs2", USIF, xrx200_pins_usif_spi_cs2), > ++GRP_MUX("stp", STP, xrx200_pins_stp), > ++GRP_MUX("nmi", NMI, xrx200_pins_nmi), > ++GRP_MUX("gpt1", GPT, xrx200_pins_gpt1), > ++GRP_MUX("gpt2", GPT, xrx200_pins_gpt2), > ++GRP_MUX("gpt3", GPT, xrx200_pins_gpt3), > ++GRP_MUX("clkout0", CGU, xrx200_pins_clkout0), > ++GRP_MUX("clkout1", CGU, xrx200_pins_clkout1), > ++GRP_MUX("clkout2", CGU, xrx200_pins_clkout2), > ++GRP_MUX("clkout3", CGU, xrx200_pins_clkout3), > ++GRP_MUX("gnt1", PCI, xrx200_pins_pci_gnt1), > ++GRP_MUX("gnt2", PCI, xrx200_pins_pci_gnt2), > ++GRP_MUX("gnt3", PCI, xrx200_pins_pci_gnt3), > ++GRP_MUX("req1", PCI, xrx200_pins_pci_req1), > ++GRP_MUX("req2", PCI, xrx200_pins_pci_req2), > ++GRP_MUX("req3", PCI, xrx200_pins_pci_req3), > ++GRP_MUX("mdio", MDIO, xrx200_pins_mdio), > ++GRP_MUX("dfe led0", DFE, xrx200_pins_dfe_led0), > ++GRP_MUX("dfe led1", DFE, xrx200_pins_dfe_led1), > ++GRP_MUX("gphy0 led0", GPHY, xrx200_pins_gphy0_led0), > ++GRP_MUX("gphy0 led1", GPHY, xrx200_pins_gphy0_led1), > ++GRP_MUX("gphy0 led2", GPHY, xrx200_pins_gphy0_led2), > ++GRP_MUX("gphy1 led0", GPHY, xrx200_pins_gphy1_led0), > ++GRP_MUX("gphy1 led1", GPHY, xrx200_pins_gphy1_led1), > ++GRP_MUX("gphy1 led2", GPHY, xrx200_pins_gphy1_led2), > ++}; > ++ > ++static const char * const xrx200_pci_grps[] = {"gnt1", "gnt2", > ++"gnt3", "req1", > ++"req2", "req3"}; > ++static const char * const xrx200_spi_grps[] = {"spi", "spi_cs1", > ++"spi_cs2", "spi_cs3", > ++"spi_cs4", "spi_cs5", > ++"spi_cs6"}; > ++static const char * const xrx200_cgu_grps[] = {"clkout0", "clkout1", > ++"clkout2", "clkout3"}; > ++static const char * const xrx200_ebu_grps[] = {"ebu a23", "ebu a24", > ++"ebu a25", "ebu cs1", > ++"ebu wait", "ebu clk", > ++"nand ale", "nand cs1", > ++"nand cle", "nand rdy", > ++"nand rd"}; > ++static const char * const xrx200_exin_grps[] = {"exin0", "exin1", "exin2", > ++"exin3", "exin4", "exin5"}; > ++static const char * const xrx200_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; > ++static const char * const xrx200_usif_grps[] = {"usif uart", "usif > uart_rts_cts", > ++"usif uart_dtr_dsr", "usif uart_dcd", > ++"usif uart_ri", > ++"usif spi", "usif spi_cs0", > ++"usif spi_cs1", "usif spi_cs2"}; > ++static const char * const xrx200_stp_grps[] = {"stp"}; > ++static const char * const xrx200_nmi_grps[] = {"nmi"}; > ++static const char * const xrx200_mdio_grps[] = {"mdio"}; > ++static const char * const xrx200_dfe_grps[] = {"dfe led0", "dfe led1"}; > ++static const char * const xrx200_gphy_grps[] = {"gphy0 led0", "gphy0 led1", > ++"gphy0 led2", "gphy1 led0", > ++"gphy1 led1", "gphy1 led2"}; > ++ > ++static const struct ltq_pmx_func xrx200_funcs[] = { > ++{"spi",ARRAY_AND_SIZE(xrx200_spi_grps)}, > ++{"usif",ARRAY_AND_SIZE(xrx200_usif_grps)}, > ++{"cgu",ARRAY_AND_SIZE(xrx200_cgu_grps)}, > ++{"exin",ARRAY_AND_SIZE(xrx200_exin_grps)}, > ++{"stp",ARRAY_AND_SIZE(xrx200_stp_grps)}, > ++{"gpt",ARRAY_AND_SIZE(xrx200_gpt_grps)}, > ++{"nmi",ARRAY_AND_SIZE(xrx200_nmi_grps)}, > ++{"pci",ARRAY_AND_SIZE(xrx200_pci_grps)}, > ++{"ebu",ARRAY_AND_SIZE(xrx200_ebu_grps)}, > ++{"mdio",ARRAY_AND_SIZE(xrx200_mdio_grps)}, > ++{"dfe",ARRAY_AND_SIZE(xrx200_dfe_grps)}, > ++{"gphy",ARRAY_AND_SIZE(xrx200_gphy_grps)}, > + }; > + > + /* --------- pinconf related code --------- */ > +@@ -733,9 +1115,6 @@ static struct gpio_chip xway_chip = { > + > + > + /* --------- register the pinctrl layer --------- */ > +-static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, > GPIO46, GPIO9}; > +-static const unsigned ase_exin_pins_map[] = {GPIO6, GPIO29, GPIO0}; > +- > + static struct pinctrl_xway_soc { > + int pin_count; > + const struct ltq_mfp_pin *mfp; > +@@ -746,21 +1125,26 @@ static struct pinctrl_xway_soc { > + const unsigned *exin; > + unsigned int num_exin; > + } soc_cfg[] = { > +-/* legacy xway */ > +-{XWAY_MAX_PIN, xway_mfp, > +-xway_grps, ARRAY_SIZE(xway_grps), > +-danube_funcs, ARRAY_SIZE(danube_funcs), > +-xway_exin_pin_map, 3}, > +-/* xway xr9 series */ > +-{XR9_MAX_PIN, xway_mfp, > +-xway_grps, ARRAY_SIZE(xway_grps), > +-xrx_funcs, ARRAY_SIZE(xrx_funcs), > +-xway_exin_pin_map, 6}, > +-/* xway ase series */ > +-{XWAY_MAX_PIN, ase_mfp, > ++/* XWAY AMAZON Family */ > ++{ASE_MAX_PIN, ase_mfp, > + ase_grps, ARRAY_SIZE(ase_grps), > + ase_funcs, ARRAY_SIZE(ase_funcs), > +-ase_exin_pins_map, 3}, > ++ase_exin_pin_map, 3}, > ++/* XWAY Danube Family */ > ++{DANUBE_MAX_PIN, danube_mfp, > ++danube_grps, ARRAY_SIZE(danube_grps), > ++danube_funcs, ARRAY_SIZE(danube_funcs), > ++danube_exin_pin_map, 3}, > ++/* XWAY xRX100 Family */ > ++{XRX100_MAX_PIN, xrx100_mfp, > ++xrx100_grps, ARRAY_SIZE(xrx100_grps), > ++xrx100_funcs, ARRAY_SIZE(xrx100_funcs), > ++xrx100_exin_pin_map, 6}, > ++/* XWAY xRX200 Family */ > ++{XRX200_MAX_PIN, xrx200_mfp, > ++xrx200_grps, ARRAY_SIZE(xrx200_grps), > ++xrx200_funcs, ARRAY_SIZE(xrx200_funcs), > ++xrx200_exin_pin_map, 6}, > + }; > + > + static struct pinctrl_gpio_range xway_gpio_range = { > +@@ -769,9 +1153,10 @@ static struct pinctrl_gpio_range xway_gp > + }; > + > + static const struct of_device_id xway_match[] = { > +-{ .compatible = "lantiq,pinctrl-xway", .data = &soc_cfg[0]}, > +-{ .compatible = "lantiq,pinctrl-xr9", .data = &soc_cfg[1]}, > +-{ .compatible = "lantiq,pinctrl-ase", .data = &soc_cfg[2]}, > ++{ .compatible = "lantiq,pinctrl-ase", .data = &soc_cfg[0]}, > ++{ .compatible = "lantiq,pinctrl-danube", .data = &soc_cfg[1]}, > ++{ .compatible = "lantiq,pinctrl-xrx100", .data = &soc_cfg[2]}, > ++{ .compatible = "lantiq,pinctrl-xrx200", .data = &soc_cfg[3]}, > + {}, > + }; > + MODULE_DEVICE_TABLE(of, xway_match); > _______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel _______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
