From: Chris R Blake <[email protected]> This patch adds the rx/tx register offsets for the qca955x SoC.
Signed-off-by: Chris R Blake <[email protected]> --- .../742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch diff --git a/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch new file mode 100644 index 0000000..2d89fd8 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch @@ -0,0 +1,14 @@ +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -1098,5 +1098,11 @@ + + #define QCA955X_ETH_CFG_RGMII_EN BIT(0) + #define QCA955X_ETH_CFG_GE0_SGMII BIT(6) ++#define QCA955X_ETH_CFG_RXD_DELAY BIT(14) ++#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3 ++#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14 ++#define QCA955X_ETH_CFG_RDV_DELAY BIT(16) ++#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3 ++#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16 + + #endif /* __ASM_MACH_AR71XX_REGS_H */ -- 2.6.2 _______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
