From: Sven Eckelmann <[email protected]> Signed-off-by: Sven Eckelmann <[email protected]> --- .../601-MIPS-ath79-add-more-register-defines.patch | 19 ++++++++++++++++++- ...-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch | 14 -------------- .../601-MIPS-ath79-add-more-register-defines.patch | 19 ++++++++++++++++++- ...-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch | 14 -------------- 4 files changed, 36 insertions(+), 30 deletions(-) delete mode 100644 target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch delete mode 100644 target/linux/ar71xx/patches-4.4/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch
diff --git a/target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch index 8bf7658..797977f 100644 --- a/target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch @@ -207,7 +207,7 @@ #define AR934X_GPIO_REG_FUNC 0x6c #define AR71XX_GPIO_COUNT 16 -@@ -560,4 +663,153 @@ +@@ -560,4 +663,170 @@ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 @@ -358,6 +358,23 @@ +#define QCA955X_GMAC_REG_ETH_CFG 0x00 + +#define QCA955X_ETH_CFG_RGMII_EN BIT(0) ++#define QCA955X_ETH_CFG_MII_GE0 BIT(1) ++#define QCA955X_ETH_CFG_GMII_GE0 BIT(2) ++#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3) ++#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4) ++#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5) +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) ++#define QCA955X_ETH_CFG_RMII_GE0 BIT(10) ++#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11) ++#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12) ++#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3 ++#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14 ++#define QCA955X_ETH_CFG_RDV_DELAY BIT(16) ++#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3 ++#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16 ++#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3 ++#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18 ++#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 ++#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch deleted file mode 100644 index 6113d2b..0000000 --- a/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -1105,5 +1105,11 @@ - - #define QCA955X_ETH_CFG_RGMII_EN BIT(0) - #define QCA955X_ETH_CFG_GE0_SGMII BIT(6) -+#define QCA955X_ETH_CFG_RXD_DELAY BIT(14) -+#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14 -+#define QCA955X_ETH_CFG_RDV_DELAY BIT(16) -+#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16 - - #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch index 8bf7658..797977f 100644 --- a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch @@ -207,7 +207,7 @@ #define AR934X_GPIO_REG_FUNC 0x6c #define AR71XX_GPIO_COUNT 16 -@@ -560,4 +663,153 @@ +@@ -560,4 +663,170 @@ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 @@ -358,6 +358,23 @@ +#define QCA955X_GMAC_REG_ETH_CFG 0x00 + +#define QCA955X_ETH_CFG_RGMII_EN BIT(0) ++#define QCA955X_ETH_CFG_MII_GE0 BIT(1) ++#define QCA955X_ETH_CFG_GMII_GE0 BIT(2) ++#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3) ++#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4) ++#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5) +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) ++#define QCA955X_ETH_CFG_RMII_GE0 BIT(10) ++#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11) ++#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12) ++#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3 ++#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14 ++#define QCA955X_ETH_CFG_RDV_DELAY BIT(16) ++#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3 ++#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16 ++#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3 ++#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18 ++#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 ++#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-4.4/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch b/target/linux/ar71xx/patches-4.4/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch deleted file mode 100644 index 6113d2b..0000000 --- a/target/linux/ar71xx/patches-4.4/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -1105,5 +1105,11 @@ - - #define QCA955X_ETH_CFG_RGMII_EN BIT(0) - #define QCA955X_ETH_CFG_GE0_SGMII BIT(6) -+#define QCA955X_ETH_CFG_RXD_DELAY BIT(14) -+#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14 -+#define QCA955X_ETH_CFG_RDV_DELAY BIT(16) -+#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16 - - #endif /* __ASM_MACH_AR71XX_REGS_H */ -- 2.7.0 _______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
