Hi! On Fri, Feb 1, 2019 at 9:53 PM Philippe Mathieu-Daudé <[email protected]> wrote: > [...] > Now that you pointed this line, I am not sure it is correct... > It maps I/O (0x01000000) region of 1B (0 0x000001) from PCI 0x00000000 > (0 0x00000000) at 0x0000000 (0x0000000) into cpu space. > But the DDR is already mapped at 0x0000000 in cpu address space... > Am I missing something? The atheros PCIE controller doesn't have an IO space at all. (at least the documentation doesn't mention it.) I'm not sure if it's possible to write a PCIE driver without IO space. I guess the existing code just uses 1 byte of system memory as a placeholder.
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