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Hello,
I'm looking at the mt7620 Ethernet driver and I see a lot of magic
happening for which I cannot find documentation anywhere. Can anybody
tell me where I can get the datasheets / programmer's guide that
document these registers please?
Examples:
I/O to 0x7830, 0x7a40 -- Entries in the WAPI table? That seems strange.
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x10cf); The mt7620
programming guide only documents 0-6, while the 802.3-2005 has
everything from 16-31 marked as "vendor specific". Also, what does port
31 do?
>From the current OpenWRT head:
static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
{
u32 i;
u32 val;
u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4),
GSW_REG_CKGCR);
/* Enable MIB stats */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1),
GSW_REG_MIB_CNT_EN);
if (mdio_mode) {
u32 val;
/* turn off ephy and set phy base addr to 12 */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(0x1f << 24) | (0xc << 16),
GSW_REG_GPC1);
/* set MT7530 central align */
val = mt7530_mdio_r32(gsw, 0x7830);
val &= ~BIT(0);
val |= BIT(1);
mt7530_mdio_w32(gsw, 0x7830, val);
val = mt7530_mdio_r32(gsw, 0x7a40);
val &= ~BIT(30);
mt7530_mdio_w32(gsw, 0x7a40, val);
mt7530_mdio_w32(gsw, 0x7a78, 0x855);
} else {
if (gsw->ephy_base) {
/* set phy base addr to ephy_base */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(gsw->ephy_base << 16),
GSW_REG_GPC1);
fe_reset(BIT(24)); /* Resets the Ethernet PHY block. */
}
/* global page 4 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x4000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x7444);
if (is_BGA)
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0114);
else
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0117);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x10cf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x6212);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0777);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 29, 0x4000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 28, 0xc077);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0000);
/* global page 3 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x3000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x4838);
/* global page 2 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x2000);
if (is_BGA) {
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0515);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0053);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aaf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x0fad);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fc1);
} else {
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0517);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0fd2);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aab);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x00ae);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fff);
}
/* global page 1 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x1000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0xe7f8);
/* turn on all PHYs */
for (i = 0; i <= 4; i++) {
val = _mt7620_mii_read(gsw, gsw->ephy_base + i, 0);
val &= ~BIT(11);
_mt7620_mii_write(gsw, gsw->ephy_base + i, 0, val);
}
}
/* global page 0 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x8000);
_mt7620_mii_write(gsw, gsw->ephy_base + 0, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 2, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 3, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 0, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 2, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 3, 4, 0x05e1);
/* global page 2 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 0, 16, 0x1111);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 16, 0x1010);
_mt7620_mii_write(gsw, gsw->ephy_base + 2, 16, 0x1515);
_mt7620_mii_write(gsw, gsw->ephy_base + 3, 16, 0x0f0f);
/* CPU Port6 Force Link 1G, FC ON */
mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
/* Set Port 6 as CPU Port */
mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
/* setup port 4 */
if (gsw->port4 == PORT4_EPHY) {
u32 val = rt_sysc_r32(SYSC_REG_CFG1);
val |= 3 << 14;
rt_sysc_w32(val, SYSC_REG_CFG1);
_mt7620_mii_write(gsw, gsw->ephy_base + 4, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 4, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 4, 16, 0x1313);
pr_info("gsw: setting port4 to ephy mode\n");
} else if (!mdio_mode) {
u32 val = rt_sysc_r32(SYSC_REG_CFG1);
val &= ~(3 << 14);
rt_sysc_w32(val, SYSC_REG_CFG1);
pr_info("gsw: setting port4 to gmac mode\n");
}
}
Thanks,
Daniel
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