Armada 370 and Tegra 2 processors have only 16 double-precision
registers. The change introduced by 8dcc1087602e ("toolchain: ARM: Fix
toolchain compilation for gcc 8.x") switched accidentally the toolchain
for mvebu cortexa9 subtarget and tegra target to cpu type with 32
double-precision registers. This stems from gcc defaults which assume
"vfpv3-d32" if only "vfpv3" as mfpu is specified. That change resulted in
unusable image, in which kernel will kill userspace as soon as causing
"Illegal instruction".Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272 Fixes: 8dcc1087602e ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") Signed-off-by: Tomasz Maciej Nowak <[email protected]> --- target/linux/mvebu/cortexa9/target.mk | 2 +- target/linux/tegra/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/mvebu/cortexa9/target.mk b/target/linux/mvebu/cortexa9/target.mk index 2a75599bc9a3..cdd4d86e4936 100644 --- a/target/linux/mvebu/cortexa9/target.mk +++ b/target/linux/mvebu/cortexa9/target.mk @@ -10,5 +10,5 @@ include $(TOPDIR)/rules.mk ARCH:=arm BOARDNAME:=Marvell Armada 37x/38x/XP CPU_TYPE:=cortex-a9 -CPU_SUBTYPE:=vfpv3 +CPU_SUBTYPE:=vfpv3-d16 KERNELNAME:=zImage dtbs diff --git a/target/linux/tegra/Makefile b/target/linux/tegra/Makefile index 0b48fc16baa2..5dd4d439849e 100644 --- a/target/linux/tegra/Makefile +++ b/target/linux/tegra/Makefile @@ -11,7 +11,7 @@ BOARD := tegra BOARDNAME := NVIDIA Tegra FEATURES := audio boot-part display ext4 fpu gpio pci pcie rootfs-part rtc squashfs usb CPU_TYPE := cortex-a9 -CPU_SUBTYPE := vfpv3 +CPU_SUBTYPE := vfpv3-d16 KERNEL_PATCHVER := 5.4 KERNEL_TESTING_PATCHVER := 5.4 -- 2.25.1 _______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/mailman/listinfo/openwrt-devel
