Hauke Mehrtens <[email protected]> [2020-06-29 00:29:22]: Hi,
> This is set in the configure_status() function: > https://elixir.bootlin.com/linux/v5.4.47/source/arch/mips/kernel/traps.c#L2125 > But I think this is not working correctly under some unknown conditions. > > I printed the read_c0_status() in the do_dsp() function and when this > exception occurs the DSPEn bit is *not* set. maybe it's due to the following: if (cpu_has_dsp) status_set |= ST0_MX; > Does someone see a bug in the broken version? No. > In this line: > 4c: 40826000 mtc0 v0,c0_status > in v0 the following bits should be set: Seems to be alright: > #define ST0_MX 0x01000000 2c: 3c040100 lui a0,0x100 << 16 = 0x01000000 > #define ST0_CU0 0x10000000 8: 3c051000 lui a1,0x1000 << 16 = 0x10000000 I think, that the problem is here, as the ST0_MX bit is set conditionally: 20: 30630010 andi v1,v1,0x10 24: 10600003 beqz v1,34 <configure_status+0x34> if (cpu_data[0].ases & 0x10) // 0x10 = MIPS_ASE_DSP #define MIPS_ASE_DSP 0x00000010 #define cpu_has_dsp __ase(MIPS_ASE_DSP) #define __ase(ase) (cpu_data[0].ases & (ase)) and then status_set doesn't have ST0_MX bit set? Just printk the status_set. -- ynezz _______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/mailman/listinfo/openwrt-devel
