Hi! On Tue, Mar 16, 2021 at 1:33 PM Ilya Lipnitskiy <[email protected]> wrote: > > TRGMII allows to run the CPU switch port 6 and GMAC0 at 1.2 Gb. This > change should improve performance. Both ER-X and ER-X-SFP have DDR3 RAM, > allowing them to take advantage of TRGMII:
NACK on patch 2/2 unless someone managed to implement audio PLL clock support for TRGMII. (I can only find a implementation in the raeth driver of the old mtk openwrt sdk based on barrier breaker, and it's writing magic values into a bunch of undocumented registers.) Not every mt7621 router using DDR3 ram can enable TRGMII. The actual requirement is the 1200MHz memory clock, because TRGMII needs an extra clock either derived from memory clock or audio PLL. Current upstream driver only implemented the former, and enabling TRGMII will break ethernet for those who replaced their bootloader or for some other reason don't have their memory running at exactly 1200MHz. I think it doesn't worth to potentially brick someone's router for this extra 200Mbps bandwidth on CPU port. -- Regards, Chuanhong Guo _______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/mailman/listinfo/openwrt-devel
