On 06.05.21 18:25, Denis Kalashnikov wrote:
What is not working:
* USB port and mPCIe slot,
* Beeper,
you will need to add kmod-gpio-beeper
+/*
+ * TODO list:
+ * - Enable beeper/buzzer,
+ * - Enable button/key,
+ * - Enable usb EHCI and export GPIOs for
+ * turning on/off power for USB port and mPCIe slot,
fyi, The GPIO nr required for the USB target (USB type A or mini pcie
slot) control is 61
+ * - Test Wi-Fi working,
+ * - Test Gigabit Ethernet working (see pll settings),
+ */
+
+/ {
+ compatible = "mikrotik,routerboard-912g";
+ model = "Mikrotik RB912G";
+};
+
+&ahb {
+ /*
+ * MFD: NAND plus GPIO-controller. They use/share SoC GPIO lines. Some
of the
+ * GPIO lines are multiplexed by a 8-bit latch (LVC573).
+ * NAND is controlled by GPIO lines (bitbang), also some NAND control
lines
+ * (nCE, ALE, CLE, READ) and data lines are multiplexed by a latch. So
driver
+ * set control lines, enable latch ("latched them") and then transfer
data.
+ * Several lines of the latch (not used for NAND control lines) are used
+ * as general-purpose GPIO. NAND ECC format is Mikrotik specific.
+ */
+ /*
+
+-----------+
+ |
|
++-----------------+ |
|
+| | |
|
+| | |
|
+| | |
| 3-4 lines
+| | |
+--------
+| G | 8 lines |
8-bit | GPIO
+| P +-------+-------------------------------------------------+
| (leds, SSR nCS)
+| I | | |
Latch |
+| O | | |
|
+| s | | |
LVC573 | 4 lines
+| | | |
+-------+
+| | | |
| |
+| | | |
| |
+| | | |
| |
+| | | |
| |
+| | | |
| |
+| | | 8
+-----------+ |
+| | |
|
+| | | l
|
+| | | i
|
+| SoC | | n
|
+| | | e
|
+| | | s
+----------------------------------+ |
+| | | |
| |
+| | | | C
| |
+| | | |
| nCE, CLE, ALE, |
+| | | | O
+----------------+
+| | | | D
| READ
+| | | | N
|
+| | | | A
|
+| | | | N A N D T
|
+| | +-----------------+ T
|
+| | | R
| nRW, RDY
+| | | A
+----------+
+| | | O
| |
+| | |
| |
+| | | L
| |
+| | |
| |
+| G | |
| |
+| P |
+----------------------------------+ |
+| I | 2 lines
|
+| O
+-----------------------------------------------------------------------+
+| s |
+| |
++-----------------+
+ Drawn on https://asciiflow.com
+ */
While it's nice info, please drop this drawing from the dts
+ nand_gpio {
+ compatible = "mikrotik,nand-gpio-latch";
+
+ /* NAND control gpios */
+ nand-read-gpios = <&gpio 3 0>; /* Read */
+ nand-rdy-gpios = <&gpio 4 0>; /* Ready */
+ nand-nrw-gpios = <&gpio 12 GPIO_ACTIVE_LOW>; /* Read/Write
Strobe */
+ nand-nce-gpios = <&gpio 13 GPIO_ACTIVE_LOW>; /* Chip Enable */
+ nand-cle-gpios = <&gpio 14 0>; /* Command Latch */
+ nand-ale-gpios = <&gpio 15 0>; /* Address Latch */
+
+ /* Latch Enable */
+ nle-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+
+ nand-data-gpios = <&gpio 0 0>,
+ <&gpio 1 0>,
+ <&gpio 2 0>,
+ <&gpio 3 0>,
+ <&gpio 4 0>,
+ <&gpio 13 0>,
+ <&gpio 14 0>,
+ <&gpio 15 0>;
+
+ latch-gpios = <&gpio 0 GPIO_ACTIVE_LOW>,
+ <&gpio 1 GPIO_ACTIVE_LOW>,
+ <&gpio 2 GPIO_ACTIVE_LOW>;
+
+ nand {
+ compatible = "mikrotik,rb91x-nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #size-cells = <1>;
+
+ /* Mikrotik second-stage bootloader */
+ partition@0 {
+ label = "booter";
+ reg = <0x0000000 0x0040000>;
+ read-only;
+ };
+
+ /* Kernel and initramfs */
+ partition@40000 {
+ label = "kernel";
+ reg = <0x0040000 0x03c0000>;
+ };
+
+ /* Read-only rootfs and user data (overlayfs) */
+ partition@400000 {
+ label = "ubi";
+ reg = <0x0400000 0x7c00000>;
+ };
+ };
+ };
Please drop the comments above from each partition. The label itself is
informative enough.
+
+ /*
+ * GPIO lines of the latch, that are not used for the NAND
+ * control lines. Used for Serial Shift register nCS and
+ * controling two LEDs: power adn user.
+ */
+ gpio_latch: gpio {
+ compatible = "mikrotik,rb91x-gpio-latch";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+};
+
Regarding this part:
+/* We just copy-past this */
+&mdio0 {
+ status = "okay";
+
+ phy-mask = <0>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+/* We just copy-paste this */
+ð0 {
+ status = "okay";
+
+ /* pll-data = <0x02000000 0x00000101 0x00001313>; */
+
+ /* mtd-mac-address = <&hard_config 0x10>; */
+
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy0>;
+
+ gmac-config {
+ device = <&gmac>;
+ rxd-delay = <3>;
+ rxdv-delay = <3>;
+ };
+};
+
Here is the info from my old 912 addition patch which:
- also enables UART
- The gmac delays required are 1 iso 3
&uart {
status = "okay";
};
&mdio0 {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ð0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
pll-data = <0x02000000 0xa0000101 0xa0001313>;
gmac-config {
device = <&gmac>;
rgmii-gmac0 = <1>;
rgmii-enabled = <1>;
rxd-delay = <1>;
txd-delay = <1>;
};
};
&wmac {
status = "okay";
qca,no-eeprom;
};
+&spi {
+ status = "okay";
+
+ /*
+ * New spi-ar934x driver (that superseeds spi-ath79 and support
+ * new shift-register mode) seems doesn't support gpio line nCS
+ * (cs-gpios) (do it?).
+ */
+ compatible = "qca,ar7100-spi";
+
+ /* Gpio nCS line for the shift register */
+ cs-gpios = <0>, <&gpio_latch 0 GPIO_ACTIVE_LOW>;
+
+ /* 64KB NOR SPI flash with routerboot and board config data */
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+
+ partitions {
+ compatible = "mikrotik,routerboot-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Mikrotik first-stage Bootloader */
+ partition@0 {
+ label = "routerboot";
+ reg = <0x0 0x0>;
+ read-only;
+ };
+
+ /*
+ * Ethernet MAC address, wireless calibration data,
+ * etc. You can read them from
+ * /sys/firmware/mikrotik/hard_config.
+ * You don't need to use rbcfg util anymore.
+ */
+ hard_config: hard_config {
+ read-only;
+ };
+
+ bios {
+ size = <0x1000>;
+ read-only;
+ };
+
+ /* Mikrotik Bootloader's Config */
+ soft_config {
+ };
+ };
+ };
+
+ /*
+ * 8-bit Shift register 74HC595 used as output GPIO chip (5 LEDs and
+ * 2 lines for turning on/off power for USB port and mPCIe slot).
+ * nCS is connected to gpio line (not to the internal SPI controller
+ * line), this line goes from the SoC through the latch.
+ */
+ ssr: ssr@1 {
+ compatible = "fairchild,74hc595";
+ gpio-controller;
+ #gpio-cells = <2>;
+ registers-number = <1>;
+ /* SPI params */
+ reg = <1>;
+ spi-max-frequency = <10000000>;
The chip used on the board is correct, and the datasheet mentions a
speed of 50MHz
+ };
+};
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+
+ led_power {
+ label = "green:power";
+ gpios = <&gpio_latch 1 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led_user {
+ label = "green:user";
+ gpios = <&gpio_latch 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ led1 {
+ label = "green:led1";
+ gpios = <&ssr 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ led2 {
+ label = "green:led2";
+ gpios = <&ssr 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ led3 {
+ label = "green:led3";
+ gpios = <&ssr 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ led4 {
+ label = "green:led4";
+ gpios = <&ssr 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ led5 {
+ label = "green:led5";
+ gpios = <&ssr 4 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ /* Is not working now -- we don't know why */
+ beeper {
+ compatible = "gpio-beeper";
+ gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* It is needed for USB port and mPCIe slot */
+&pcie {
+ status = "okay";
+};
+
+/* SoC Wi-Fi MAC managed by ath9k driver (RB912UAG-2HPnD) */
+&wmac {
+ status = "okay";
+ /*
+ * Wireless calibration data is in SPI NOR flash
+ * hard_config partition. In OpenWrt you can also
+ * read it from sysfs file
+ * /sys/firmware/mikrotik/hard_config/wlan_data
+ * from offset 0x1000
+ * (/etc/hotplug.d/firmware/10-ath9k-eeprom script
+ * does this).
+ */
+ qca,no-eeprom;
+};
diff --git a/target/linux/ath79/image/mikrotik.mk
b/target/linux/ath79/image/mikrotik.mk
index 74f8603b5a..b9c21dab7d 100644
--- a/target/linux/ath79/image/mikrotik.mk
+++ b/target/linux/ath79/image/mikrotik.mk
@@ -1,5 +1,14 @@
include ./common-mikrotik.mk
+define Device/mikrotik_routerboard-912g
+ $(Device/mikrotik_nand)
+ SOC := ar9342
+ DEVICE_MODEL := RouterBOARD 912G
+ DEVICE_PACKAGES += kmod-usb-ehci kmod-usb2
add kmod-gpio-beeper
I'll test some more later on.
Regards,
Koen
_______________________________________________
openwrt-devel mailing list
[email protected]
https://lists.openwrt.org/mailman/listinfo/openwrt-devel
