Thank you, Andre. I'v fixed it. https://patchwork.ozlabs.org/project/openwrt/patch/meapr01mb3574140e649a556be964a3bec0...@meapr01mb3574.ausprd01.prod.outlook.com/
Regards, Sean On 2021/9/14 15:20, Andre Heider wrote: > On 13/09/2021 10:44, sean lee wrote: >> bump version and remove patches that have been applied >> >> 176d701 wtmi: Wait 1s after putting PHYs INTn pin low >> 2eeccfe wtmi: Change comment describing reset workaround >> e8c94a5 wtmi: Count RAM size from both CS0 and CS1 >> 995979e wtmi: Rename macro >> e29eb29 wtmi: soc: Fix start_ap_workaround() for TF-A with debug >> 81245ed wtmi: Use constant name PLAT_MARVELL_MAILBOX_BASE >> 18ccb83 wtmi: Do a proper UART reset with clock change as described in spec >> 15ff106 avs: Validate VDD value from OTP >> 3f33626 fix: clock: a3700: change pwm clock for 600/600 and 1200/750 preset >> fb5e436 wtmi: uart: fix UART baudrate divisor calculation >> >> Signed-off-by: sean lee <i...@live.com> > > Nice, but the patch seems misformatted and doesn't apply. > > patchwork doesn't like it too, parts fail to parse: > http://patchwork.ozlabs.org/project/openwrt/patch/meapr01mb3574e3f34ba95dc3e8802a9dc0...@meapr01mb3574.ausprd01.prod.outlook.com/ > > Cheers, > Andre _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
