Arınç ÜNAL <arinc.u...@arinc9.com> writes: > My theory is that the Mediatek SDK ethernet driver run from the > bootloader on these devices must be configured to enable the rgmii2 > pins. The bootloader on the mt7621a board I tested didn't configure > the rgmii bus or GE2 (second GMAC of the SoC) at all.
I'm not claiming to understand this.. But according to the pseudo-datasheet I got for MT7621, the "Normal mode" for most pins is the SoC function (e.g rgmii2) and not gpio. This maps to setting the associated mode register selector bit(s) to 0. Which I believe is the default state? My interpretation is that the pins will be configured for rgmii2 unless something explicitly sets them to gpio. So I'd say rgmii2 should work unless the bootloader messed up things for us. But of course, explicit mapping is even safer. So by all means, merge this patch set. Just wondered about the "will start working" statement. Bjørn _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel