#19620: RTL8306.c
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Reporter: anonymous | Owner: developers
Type: defect | Status: new
Priority: normal | Milestone: Chaos Calmer (trunk)
Component: packages | Version: Trunk
Keywords: |
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#define RTL8306_NUM_VLANS 16
#define RTL8306_NUM_PORTS 6
#define RTL8306_PORT_CPU 5
#define RTL8306_NUM_PAGES 4
#define RTL8306_NUM_REGS 32
This is wrong based on this page
http://wiki.openwrt.org/toh/linksys/wrt160nl (RTL8306S or SD)
Yet, the switch has two RMII pools, one 4 ports for ETH0 and another 2
ports for ETH1 based on the Data Sheet for RTL8306/8. Should there be 2
whole switches based on the OS or is the OS just confused with the switch
features. I don't know but something is definitely confused cause the CPU
is on port 4 and it reports it as the WAN.
So for for this router the switch0 the CPU port should be on port 4, I am
not sure on the rest. So
I change the CPU port in the code, yet I am unsure on how to go about the
second RMII.
Any help would be great!
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Ticket URL: <https://dev.openwrt.org/ticket/19620>
OpenWrt <http://openwrt.org>
Opensource Wireless Router Technology
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