Hi Partners, Kindly let me know if you have any consultant for the following position.
*Please respond back with an updated resume and all inclusive rates to [email protected] <[email protected]>* *Position: ASIC Physical Design/Structural Design Engineer* *Location: Oregon OR /Santa Clara, CA* *Duration: 6 months * *Skills Preferred* · Expertise in Netlist to GDS flow which includes Synthesis, Layout (Floorplan, Place and Route, CTS (clock tree synthesis) and Static Timing Analysis, · Desired Tools Experience: Synopsys ICC flow, Prime Time, Design Compiler, Redhawk, LEC/Formailty, and Caliber. · Work experience in 45nm, 22nm, 14nm, or lower process technology · Good knowledge of digital design concepts · Good knowledge of ASIC design flow · Good team player and ability to work with stakeholders like RTL team, DFT team and verification teams · Good hands on knowledge of Planning and execution at block level and Full chip level *Qualifications Basic* Bachelor's degree or Master's Degree in Electronics/VLSI/Electrical Engineering At least 4 -10 years of experience with below skills set Thanks & Regards *Raja* Burgeon IT Services LLC Phone No. : 302-338-9683; 302-220-4724, Fax : 302-355-1559 Email: [email protected] Website: www.burgeonits.com -- You received this message because you are subscribed to the Google Groups "Oracle-Projects" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at http://groups.google.com/group/oracle-projects. For more options, visit https://groups.google.com/groups/opt_out.
