*Greetings!*
Our Direct Client has an urgent requirement for *"* *FPGA / ASIC Design Verification" *for their Long term project in *"San Jose, CA".*....Please submit resumes at - *[email protected] <[email protected]> * *Title:* FPGA / ASIC Design Verification *Location:* San Jose, CA *Duration:* 6 Months * Job Description:* * Expertise in *Field-Programmable Gate Array (FPGA)* / *Application-Specific Integrated Circuit (ASIC)* design, verification, design partitioning automation, integration, synthesis, implementation, timing closure * Expertise in Symplify synthesis tools, Altera/Xilinix P&R tools, * Well versed with Xilinx (Vertex5/6) or Altera (Stratix4/5) FPGA architecture * Experience in FPGA & Silicon board bring up activity * Experience in using equipments such as Logic Analyzer, Oscilloscope * Experience in Verilog HDL & Scripting languages such as Make flow, Perl/ TCL * Experience with any design partitioning tool * Have strong debugging & trouble shooting skills *Warm Regards,* *Viduth* *(Vidu)* *First Tek, Inc.* 1551 S Washington Avenue, Suite 402 A, Piscataway, NJ 08854 *[email protected] <[email protected]>* | *www.first-tek.com <http://www.first-tek.com>* Direct: 732-328-2287 732-32 *Ranked 31st on Deloitte 2008 NY, NJ, CT Technology Fast 50* *A 2007 Inc 500 winner for 2004-2006* *A 2007 NJ Finest winner for 2004-2006* *Ranked 4th on Deloitte 2007 Technology Fast 50 for 2002-2006* Call Send SMS Add to Skype You'll need Skype CreditFree via Skype -- You received this message because you are subscribed to the Google Groups "Oracle-Projects" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at http://groups.google.com/group/oracle-projects. For more options, visit https://groups.google.com/groups/opt_out.
