Hi --

I'm trying to understand the sampling and decimation structure of the RTL-SDR dongle, to work out the effective number of bits after decimation.

From Google and looking at the librtlsdr code (which is beyond my programming depth), I think I've figured out the following. I'd much appreciate verification/correction/amplification.

1. Actual ADC in the RTL-2832U is a single-bit sigma-delta running at some very high rate.

2.  This is converted to 28.8 msps at 8 bit depth.

3. 28.8 msps is downsampled to the rate requested by the user and sent over the USB bus as 8 bit unsigned IQ pairs.

Based on that, I *think*:

a. Any processing gain in the downsample from 28.8 msps/8 bits within the chip is lost because the wire samples are limited to 8 bits. The output is 8 bits dynamic range regardless of the sample rate set.

b. THEREFORE... for best dynamic range one wants to set the RTL-2832U to the highest sample rate that avoids lost samples, and do further decimation in the host processor, where the added bits aren't lost on the wire.

I'd appreciate any verification or correction of that analysis.


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