On Sun, Dec 11, 2016 at 10:08 AM, Avi Kivity <[email protected]> wrote:

>
>
>
>
>> the 128 TB virtual address space), extend the physical RAM limit to
>> 8 PB and the virtual address space to 64 PB using la57 addressing.
>>
>> TODO: compile- and run- time switch to support pre-la57 processors.
>> ---
>>
>> Note: requires qemu patch to emulate la57.
>>
>
> Thanks Avi, this is a really interesting (and unexpected) patch.
>
> Apparently Intel only released the white paper about 5-level page tables
> this month (https://software.intel.com/sites/default/files/managed/
> 2b/80/5-level_paging_white_paper.pdf) and Linux patches were released 2
> days ago, so you were pretty fast about this patch. Cool :-)
>
>
> Just showing off the power of out template-based mmu instantiating the
> code for the fifth level automatically.
>

By the way, another reason why we must NOT switch to this 57-bit virtual
addresses automatically, even if supported by the host (unless the size of
the physical memory doesn't necessitate it),  is that some user-space code,
which has gotten used to all the free bits in pointers, might be (ab)using
it and will fail with the new 57-bit addresses. One example given in the
Linux patches for LA57 is some unnamed JIT compiler. My own example is
Boost's tagged_ptr, which assumes it has 16 free bits in pointers to put
stuff in (note that this particular code is already broken on Osv for
another reason - see https://svn.boost.org/trac/boost/ticket/10616). Who
knows what else makes this assumption.

Alternatively, we could switch to 57-bit addresses when available, but just
try hard not to *use* more than 48 bits until absolutely necessary. I'm not
sure how easy it would do that with our memory allocater that divides the
virtual address space. Probably not really worth the effort, as
applications will eventually clean up their act when this LA57 thing gets
into Linux and starts getting used.

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