On Fri, Nov 30, 2018 at 11:06 PM Waldek Kozaczuk <[email protected]>
wrote:

> In this issue
> https://github.com/cloudius-systems/osv/issues/827#issuecomment-271140573 
> Nadav
> points out that for whatever reason we are NOT initializing FPU control set
> in init_fpu(). I think that by default FNINIT operation does set it to this
> value - *0x037f *- which per this (
> https://sites.uclouvain.be/SystInfo/usr/include/fpu_control.h.html) sets
> double extended precision, nearest rounding control and masks all FPU
> exceptions.
>

Correct. I came to exactly the same conclusions in
https://github.com/cloudius-systems/osv/issues/828.



>
> But I think it would not hurt to set this explicitly (I looked up the
> FreeBSD code which does this).
>

I agree. Would be nice to have a comment saying that this is FNINIT's
default anyway. Also would be nice not to use these ugly numbers but macros
- for example, in https://github.com/cloudius-systems/osv/issues/828 I
noted that 0x1f80 is (FE_ALL_EXCEPT << 7).

By the way, in the past you suggested we can enable "fpu stack overflow"
exceptions. But how? I see (in fenv.h) we have the following bits:
#define FE_INVALID    1
#define __FE_DENORM   2
#define FE_DIVBYZERO  4
#define FE_OVERFLOW   8
#define FE_UNDERFLOW  16
#define FE_INEXACT    32

Which one of these says anything about stack overflow?


> diff --git a/arch/x64/processor.hh b/arch/x64/processor.hh
> index a26fb028..142742ca 100644
> --- a/arch/x64/processor.hh
> +++ b/arch/x64/processor.hh
> @@ -391,7 +391,9 @@ inline u64 read_xcr(u32 reg)
> inline void init_fpu()
> {
>     asm volatile ("fninit" ::: "memory");
> -    unsigned int csr = 0x1f80;
> +    u16 cw = 0x037f;
> +    asm volatile ("fldcw %0" : : "m" (cw));
> +    u32 csr = 0x1f80;
>     asm volatile ("ldmxcsr %0" : : "m" (csr));
> }
>
>
> What do you think?
>
> Waldek
>
> PS. The diff above also changes csr type to u32 to make it consistent to
> changes made by this patch -
> https://github.com/cloudius-systems/osv/commit/d5cf37af8be57beed4c78c7fa95ac135d96640e8
> - adding capability for feenableexcept
>

Yes, makes sense.

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