On Saturday, March 20, 2021 at 2:20:47 AM UTC-4 Pekka Enberg wrote:
> On Fri, Mar 19, 2021 at 11:50 PM Waldemar Kozaczuk <jwkoz...@gmail.com> > wrote: > >> The AArch64 Programmer's Guides Generic Timer (chapter 3.4, page 10) >> states following: >> >> "The interrupts generated by the timer behave in a level-sensitive manner. >> This means that, once the timer firing condition is reached, >> the timer will continue to signal an interrupt until one of the >> following situations occurs: >> - IMASK is set to one, which masks the interrupt. >> - ENABLE is cleared to 0, which disables the timer. >> - TVAL or CVAL is written, so that firing condition is no longer met." >> >> This indicates that the timer interrupt handler needs to mask >> or disable the timer, otherwise the interrupt will be re-delivered >> and in some scenarios might cause underlying VMM (like QEMU in TCG mode) >> stop delivering subsequent interrupts. In any case per the description >> from the guide above, it is correct to mask the interrupt and/or disable >> the timer in the timer interrupt handler. This is also what Linux does - >> >> https://github.com/torvalds/linux/blob/edd7ab76847442e299af64a761febd180d71f98d/drivers/clocksource/arm_arch_timer.c#L638-L652 >> . >> > > Reviewed-by: Pekka Enberg <pen...@scylladb.com> > > >> >> Besides the above, the patch also sligthly optimizes the method set() >> to make it set new timer only if calculated number of ticks (tval) >> is greater than 0. >> > > Why is this optimization useful/needed? > It saves us some unnecessary interruptions - not a big win. > > - Pekka > -- You received this message because you are subscribed to the Google Groups "OSv Development" group. To unsubscribe from this group and stop receiving emails from it, send an email to osv-dev+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/osv-dev/910bdcdb-a32f-47a2-959d-a624c0558196n%40googlegroups.com.
