Regards _Sugesh
> -----Original Message----- > From: Yuanhan Liu [mailto:[email protected]] > Sent: Thursday, September 14, 2017 4:19 AM > To: Darrell Ball <[email protected]> > Cc: Finn Christensen <[email protected]>; Chandran, Sugesh > <[email protected]>; [email protected] > Subject: Re: [ovs-dev] [PATCH v2 8/8] netdev-dpdk: set FDIR config > > On Wed, Sep 13, 2017 at 01:57:22AM +0000, Darrell Ball wrote: > > > > > > On 9/11/17, 1:14 AM, "[email protected] on behalf of > Finn Christensen" <[email protected] on behalf of > [email protected]> wrote: > > > > -----Original Message----- > > From: [email protected] [mailto:ovs-dev- > [email protected]] On Behalf Of Yuanhan Liu > > Sent: 11. september 2017 09:55 > > To: Chandran, Sugesh <[email protected]> > > Cc: [email protected] > > Subject: Re: [ovs-dev] [PATCH v2 8/8] netdev-dpdk: set FDIR config > > > > On Mon, Sep 11, 2017 at 07:42:57AM +0000, Chandran, Sugesh wrote: > > > > > > > > > Regards > > > _Sugesh > > > > > > > > > > -----Original Message----- > > > > From: [email protected] [mailto:ovs-dev- > > > > [email protected]] On Behalf Of Yuanhan Liu > > > > Sent: Tuesday, September 5, 2017 10:23 AM > > > > To: [email protected] > > > > Subject: [ovs-dev] [PATCH v2 8/8] netdev-dpdk: set FDIR config > > > > > > > > From: Finn Christensen <[email protected]> > > > > > > > > The Intel i40e PMD driver requires the fdir mode set to > > > > RTE_FDIR_MODE_PERFECT, otherwise, the flow creation would be > failed. > > > [Sugesh] this means it doesn't honor the flow masks which passed onto > rte_flow_*? > > > > IIRC, that's what I found after divig the code. It's an issue > > reported/fixed > by Finn. I also don't have the nic for testing. > > > > [Finn] Yes, this was needed to make our test setup using an XL710 work, > with the rte_flow implementation. > > It's a while ago so I don't exactly remember how we ended up with this > solution. However, we are definitely not > > Intel XL710 experts, so there might be other ways to achieve the > rte_flow functionality. > > This issue, and problem raised about the overall change in configuration > impact on NICs using this setting (Napatech > > does not use it), I think should be reviewed/verified by NIC vendors > using it. > > > > > > [Darrell] We need to confirm the masking in the flow (but from what I see, > it is ignored as Sugesh mentioned), > > which would be a significant difference. > > I guess we need input from Intel flow director folks to be > > sure and > check if this can be done otherwise. > > What about the 82599 as another example ? > > > I will leave this to Intel folks. [Sugesh] From the 82599 datasheet ======= The 82599 support two types of filtering modes (static setting by the FDIRCTRL.PerfectMatch bit): * Perfect match filters - The hardware checks a match between the masked fields of the received packets and the programmed filters. Masked fields should be programmed as zeros in the filter context. The 82599 support up to 8 K - 2 perfect match filters. * Signature filters - The hardware checks a match between a hash-based signature of the masked fields of the received packet. The 82599 supports up to 32 K - 2 signature filters. * Notation - The Perfect Match fields and Signature field are denoted as Flow ID fields. The 82599 supports masking / range for the previously described fields. These masks are defined globally for all filters in the FDIR...M register. ======= So my understanding is even if it can support masking, the mask is global and not per flow. Again I will confirm this and provide more details. > > --yliu _______________________________________________ dev mailing list [email protected] https://mail.openvswitch.org/mailman/listinfo/ovs-dev
