On 13.11.2019 18:01, Malvika Gupta wrote:
> The accurate timing implementation in this patch gets the wall clock counter
> via
> cntvct_el0 register access. This call is portable to all aarch64 architectures
> and has been verified on an 64-bit arm server.
>
> Suggested-by: Yanqin Wei <[email protected]>
> Signed-off-by: Malvika Gupta <[email protected]>
> ---
Thanks for the patch!
Are you trying to use AF_XDP on aarch64? Asking because it's the only
real scenario where this patch can be useful.
For the patch subject, I'd suggest to shorten it a little.
'timing', 'TSC' and 'cycle counter' are kind of synonyms here and doesn't
make the sentence any clear. Suggesting something like this:
"dpif-netdev-perf: Accurate cycle counter update on aarch64."
What do you think?
One more comment inline.
> lib/dpif-netdev-perf.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/lib/dpif-netdev-perf.h b/lib/dpif-netdev-perf.h
> index ce369375b..4ea7cc355 100644
> --- a/lib/dpif-netdev-perf.h
> +++ b/lib/dpif-netdev-perf.h
> @@ -220,6 +220,11 @@ cycles_counter_update(struct pmd_perf_stats *s)
> asm volatile("rdtsc" : "=a" (l), "=d" (h));
>
> return s->last_tsc = ((uint64_t) h << 32) | l;
> +#elif !defined(_MSC_VER) && defined(__aarch64__)
> + uint64_t tsc;
> + asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
> +
> + return s->last_tsc = tsc;
I think we could drop the 'tsc' local variable here and write
directly to s->last_tsc. Less number of variables and operations.
Best regards, Ilya Maximets.
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