Hi Harry, Thanks for the patch, I learn a lot from them.
On Wed, May 6, 2020 at 6:05 AM Harry van Haaren <[email protected]> wrote: > > This patchset implements the changes as proposed during the > OVS Conf '19, in the talk "Next steps for SW Datapath". > Youtube link: https://youtu.be/x0bOpojnpmU > > The talk raises 3 main requirements for CPU ISA Optimizations, > each of which is addressed in some of the patches below. > - Test & Validation (video @ 2:20) > - Usabiliity & Debug (video @ 6:00) > - Package & Deploy (video @ 8:45) > > Patch 1/5: > The test and validation requirements proposed above are implemented, > with the refactor of the subtable function pointer registration, > and the autovalidator implementation is added. > > Patch 2/5: > Adds the commands for usability & debug. > > Patch 3/5: > Enable CPU ISA detection at runtime, providing information for future > ISA optimized functions. v1 for CPU ISA: > https://patchwork.ozlabs.org/series/160427/mbox/ > > Patch 4/5: > Build system changes to enable the Package & Deploy requirements, > allowing a single OVS binary to run on all CPUs, but also gain best > performance from CPU specific ISA optimizations. > > Patch 5/5: > Actual AVX-512 implementation for DPCLS subtable search. This is the > actual SIMD vector code, which performs DPCLS miniflow iteration in > parallel. > >From your previous slides and patch5, I roughly understand the avx code logic. I'm also thinking about a very rough idea. I wonder if it is possible to use avx scatter function to implement miniflow_expand. And for lookup a subtable, we can expand to the origin "struct flow" memory layouts for both packets and subtable->mf. So each field for each packet is at a fixed offset from the mf values. This wastes some memory due to expand but makes rule match keys easier? Regards, William _______________________________________________ dev mailing list [email protected] https://mail.openvswitch.org/mailman/listinfo/ovs-dev
