I do, yes. I'm using pf as the dhcp for the reg and iso VLANS. I know dhcpd is working correctly, as if I manually put a port into the registration VLAN using the switch CLI it picks up an IP in the registration range.
Thanks, Mark -----Original Message----- From: Manueco, Antonio [mailto:[email protected]] Sent: 21 February 2011 03:05 To: [email protected] Subject: Re: [Packetfence-users] Fwd: VLAN assignment and DHCP Do you have a DHCP server listening on that VLAN? -Antonio Manueco Sent via Mobile. On Feb 20, 2011, at 7:04 PM, Mark Holmes <[email protected]> wrote: > > Anyone have any thoughts on this? > > Thanks, > > Mark > > From: Mark Holmes > <[email protected]<mailto:[email protected]>> > Date: 18 February 2011 09:37:11 GMT > To: > "'[email protected]<mailto:[email protected]>'" > > <[email protected]<mailto:[email protected]>> > Subject: [Packetfence-users] VLAN assignment and DHCP > Reply-To: > "[email protected]<mailto:[email protected]>" > > <[email protected]<mailto:[email protected]>> > > Hi all, > > I have got Packetfence set up, it's putting ports into the various VLANS > (registration, main network etc) correctly but then once the port has > changed, nothing happens and the DHCP request times out. > > I'm using port security as that is supported with this switch (a 3Com 4200G) > > > For example > ----------- > Connect new machine > > Port put into VLAN 50 by PF (registration VLAN) - I confirm this on the switch > > But no answer from DHCP on registration network (dhcpd running on PF) > > Same if I register the machine (via the admin console) and put plug it in - > the port goes into the correct VLAN, but DHCP doesn't get an answer. > > Running tcpdump on the registration interface shows no dhcp request is > received on the registration interface of the PF box. > > If I manually put another port into the registration VLAN and plug into that, > it gets an IP from the reg subnet and when I then open a browser the > registration page appears - so the dhcpd is configured correctly etc. > > Any ideas, anyone? > > Cheers, > > Mark > > > > > ------------------------------------------------------------------------------ > The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: > Pinpoint memory and threading errors before they happen. > Find and fix more than 250 security defects in the development cycle. > Locate bottlenecks in serial and parallel code that limit performance. > http://p.sf.net/sfu/intel-dev2devfeb > _______________________________________________ > Packetfence-users mailing list > [email protected]<mailto:[email protected]> > https://lists.sourceforge.net/lists/listinfo/packetfence-users > ------------------------------------------------------------------------------ > The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: > Pinpoint memory and threading errors before they happen. > Find and fix more than 250 security defects in the development cycle. > Locate bottlenecks in serial and parallel code that limit performance. > http://p.sf.net/sfu/intel-dev2devfeb > _______________________________________________ > Packetfence-users mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/packetfence-users ------------------------------------------------------------------------------ The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: Pinpoint memory and threading errors before they happen. Find and fix more than 250 security defects in the development cycle. Locate bottlenecks in serial and parallel code that limit performance. http://p.sf.net/sfu/intel-dev2devfeb _______________________________________________ Packetfence-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/packetfence-users ------------------------------------------------------------------------------ The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: Pinpoint memory and threading errors before they happen. Find and fix more than 250 security defects in the development cycle. Locate bottlenecks in serial and parallel code that limit performance. http://p.sf.net/sfu/intel-dev2devfeb _______________________________________________ Packetfence-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/packetfence-users
