I'm sure Palm has already worked all this out, but in case any of the
results are surprising, I thought I'd ask so I can begin preparations.
My impression of the standard ARM core (and maybe Palm has found a
variant) is that:
(1) Big Endian mode only has second class support, i.e., swap on
load/store
(2) 32-bit word accesses must occur on 32-bit aligned boundaries.
Obviously, if either of these points remains, the implications are
staggering: all applications need to be recompiled, all pre-existing
databases need to be migrated, and all programs must be debugged for
every instance of the logical equivalent of a union.
Also, while this would have a slight hit on cost, I certainly hope Palm
is going for a 32-bit bus to the data and instruction caches and as wide
a bus as possible from cache to ram. The whole key to getting
performance at low power is low frequency / high bus width - and you're
gonna need as much memory bandwidth as possible to feed those high MHz
ARMs. :) Of course, this is assuming the primary goal of the migration
effort is for future performance and not merely for better CPU supplies.
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