On Wed, 15 Dec 2004 09:46:00 -0800, Ron Nicholson <[EMAIL PROTECTED]> wrote: > On Wed, 15 Dec 2004 07:34:37, Jorge Acereda writes: > >How can I sync/invalidate the i-cache and d-cache in OS 5? > > On older OS 5 devices which run applications in supervisor > mode, one can use the MCR ARM instruction, although you have > to make sure the code containing this instruction was locked > down long enough in the past for it not to be stale in cache itself > (shortly after reset time, for instance). > > Many newer OS 5 devices seem to automatically invalidate > icache and flush dcache on every PaceNativeCall, whether > or not this is needed (on subsequent calls to locked armlets, > for instance), which can be a performance problem.
I am using Peal to call my ARM code. I have been able to call generated code with another method. Instead of having the generated code in a BSS section (static char generated[GENERATED_SIZE];), I allocated memory with MemGluePtrNew(). It works perfectly without calling the 68k part. Does that mean that MemGluePtrNew() memory is marked as non-cacheable or write-through or something like that? TIA, Jorge Acereda -- For information on using the Palm Developer Forums, or to unsubscribe, please see http://www.palmos.com/dev/support/forums/
