On Sat, Jan 16, 2010 at 09:59:23PM +0300, Alexander Chemeris wrote:
> Hi,
>
> flexrf_base::_refclk_freq() just repeats old version of
> db_base::_refclk_freq() with fixed fpga frequency. We can safely
> remove implementation from flexrf_base, because base class implements
> it correctly, using runtime FPGA clock frequency value:
>
> double
> db_base::_refclk_freq()
> {
> return usrp()->fpga_master_clock_freq() / _refclk_divisor();
> }
>
> This fix allows Python examples to work correctly with non-64e6 clock
> and RFX DBs.
>
> --
> Regards,
> Alexander Chemeris.
Thanks!
Eric
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