diff --git a/grc/blocks/usrp_simple_sink_x.xml b/grc/blocks/usrp_simple_sink_x.xml
index b52cd48..838b311 100644
--- a/grc/blocks/usrp_simple_sink_x.xml
+++ b/grc/blocks/usrp_simple_sink_x.xml
@@ -8,7 +8,7 @@
 	<name>USRP Sink</name>
 	<key>usrp_simple_sink_x</key>
 	<import>from grc_gnuradio import usrp as grc_usrp</import>
-	<make>grc_usrp.simple_sink_$(type.fcn)(which=$which, side=$side)
+	<make>grc_usrp.simple_sink_$(type.fcn)(which=$which, side=$side#if $fpga_clock_freq()>0 then ', fpga_freq='+str($fpga_clock_freq()) else ''#)
 self.$(id).set_interp_rate($interpolation)
 self.$(id).set_frequency($frequency, verbose=True#slurp
 #if $lo_offset() != float('inf')
@@ -51,6 +51,12 @@ self.$(id).set_auto_tr(True)
 		<type>int</type>
 	</param>
 	<param>
+		<name>USRP clock (Hz)</name>
+		<key>fpga_clock_freq</key>
+		<value>0</value>
+		<type>int</type>
+	</param>
+	<param>
 		<name>Interpolation</name>
 		<key>interpolation</key>
 		<type>int</type>
@@ -121,7 +127,10 @@ self.$(id).set_auto_tr(True)
 		<type>$type</type>
 	</sink>
 	<doc>
-The USRP sink inputs 128 Megasamples per second / interpolation.
+The USRP sink inputs 2 * USRP frequency / interpolation samples per second.
+If you use USRP with stock clock, you can set according setting to 0, which \
+means default. If your USRP has non-default clock, you need to set "USRP \
+clock" setting to appropriate value in Hz.
 
 Input amplitude should be between 0 and 32767.
 
diff --git a/grc/blocks/usrp_simple_source_x.xml b/grc/blocks/usrp_simple_source_x.xml
index 7fcc7a2..f22e775 100644
--- a/grc/blocks/usrp_simple_source_x.xml
+++ b/grc/blocks/usrp_simple_source_x.xml
@@ -8,7 +8,7 @@
 	<name>USRP Source</name>
 	<key>usrp_simple_source_x</key>
 	<import>from grc_gnuradio import usrp as grc_usrp</import>
-	<make>grc_usrp.simple_source_$(type.fcn)(which=$which, side=$side, rx_ant=$rx_ant#if $hb_filters() then ', no_hb=True' else ''#)
+	<make>grc_usrp.simple_source_$(type.fcn)(which=$which, side=$side, rx_ant=$rx_ant#if $hb_filters() then ', no_hb=True' else ''##if $fpga_clock_freq()>0 then ', fpga_freq='+str($fpga_clock_freq()) else ''#)
 #if $format()
 self.$(id).set_format(width=$format.width, shift=$format.shift)
 #end if
@@ -67,6 +67,12 @@ self.$(id).set_gain($gain)</make>
 		<type>int</type>
 	</param>
 	<param>
+		<name>USRP clock (Hz)</name>
+		<key>fpga_clock_freq</key>
+		<value>0</value>
+		<type>int</type>
+	</param>
+	<param>
 		<name>Decimation</name>
 		<key>decimation</key>
 		<type>int</type>
@@ -153,7 +159,10 @@ self.$(id).set_gain($gain)</make>
 		<type>$type</type>
 	</source>
 	<doc>
-The USRP source outputs 64 Megasamples per second / decimation.
+The USRP source outputs USRP frequency / decimation samples per second.
+If you use USRP with stock clock, you can set according setting to 0, which \
+means default. If your USRP has non-default clock, you need to set "USRP \
+clock" setting to appropriate value in Hz.
 
 The "Receive Antenna Setting" selects one of the SMA connectors as the data source. \
 Flex RF boards use the "TX/RX" and "RX2" settings. \
diff --git a/grc/grc_gnuradio/usrp/simple_usrp.py b/grc/grc_gnuradio/usrp/simple_usrp.py
index fb7a395..1234896 100644
--- a/grc/grc_gnuradio/usrp/simple_usrp.py
+++ b/grc/grc_gnuradio/usrp/simple_usrp.py
@@ -27,13 +27,14 @@ from gnuradio import gr
 class _simple_source(gr.hier_block2):
 	"""A single usrp source of IO type short or complex."""
 
-	def __init__(self, which, side='A', rx_ant='RXA', no_hb=False):
+	def __init__(self, which, side='A', rx_ant='RXA', no_hb=False, fpga_freq=None):
 		"""
 		USRP simple source contructor.
 		@param which the unit number
 		@param side the usrp side A or B
 		@param rx_ant the antenna choice
 		@param no_hb disable half band filters
+		@param fpga_freq USRP reference frequency (None for default)
 		"""
 		self._no_hb = no_hb
 		#initialize hier2 block
@@ -49,6 +50,10 @@ class _simple_source(gr.hier_block2):
 		self._get_u().set_mux(self._get_u().determine_rx_mux_value(subdev_spec))
 		self._subdev = self._get_u().selected_subdev(subdev_spec)
 		if common.is_flex(rx_ant): self._subdev.select_rx_antenna(rx_ant)
+		#set FPGA reference frequency
+		if fpga_freq is not None:
+			self._get_u().set_fpga_master_clock_freq(long(fpga_freq))
+			print "fpga_master_clock_freq() = ", self._get_u().fpga_master_clock_freq()
 		#connect
 		self.connect(self._get_u(), self)
 
@@ -75,11 +80,12 @@ class simple_source_s(_simple_source, common.usrp_source_s): pass
 class _simple_sink(gr.hier_block2):
 	"""A single usrp sink of IO type short or complex."""
 
-	def __init__(self, which, side='A'):
+	def __init__(self, which, side='A', fpga_freq=None):
 		"""
 		USRP simple sink contructor.
 		@param which the unit number
 		@param side the usrp side A or B
+		@param fpga_freq USRP reference frequency (None for default)
 		"""
 		#initialize hier2 block
 		gr.hier_block2.__init__(
@@ -92,6 +98,9 @@ class _simple_sink(gr.hier_block2):
 		subdev_spec = common.to_spec(side)
 		self._get_u().set_mux(self._get_u().determine_tx_mux_value(subdev_spec))
 		self._subdev = self._get_u().selected_subdev(subdev_spec)
+		#set FPGA reference frequency
+		if fpga_freq is not None:
+			self._get_u().set_fpga_master_clock_freq(long(fpga_freq))
 		#connect
 		self.connect(self, self._get_u())