*Validation/Verification Engineer Jobs – C2C*
*GENERAL INFORMATION:* Location: Bayarea, CA Duration: 1-2 years Job type: Contract Pay-terms: C2C/1099 Priority: Very High Visa: Open Level: Senior Rate: $40-$50/hr You can apply for one or multiple positions at the same time. Each requirement determines specific role as per the skills and will be appointed to that particular team if shortlisted. Required skills/experience is given under each requirement title. *REQUIREMENTS LIST: * *REQUIREMENT1*: Validation/Verification Engineer : UVM , PCIe 6+ years exp *REQUIREMENT2:*Validation/Verification Engineer : UVM , Compression Logic Lz77 Algorithm experience , 6+ years *REQUIREMENT3*: Validation/Verification Engineer : Ethernet-MAC , UVM and 6+ years experience *REQUIREMENT4*: CAD Engineer: Develop and deploy RTL tools and methodologies for IP development; Develop and deploy software to enable IPs for Quartus; Reference Design; Reference design building through Quartus, basic validation and testing on hardware. Designs to support protocols like Pcie, Ethernet, Interlaken, CPRI etc; Other areas for contractor Requirements . *REQUIREMENT5*. User Mode driver (UMD) development Hand-on experience in software distribution and installation; Hand-on experience in C/C++; Develop / port driver; Integrate UMD with AAL (Intel Accelerator Abstract Layer) interface *REQUIREMENT6*. Design development and FPGA integration Hand-on experience in all C, SystemVerilog, SystemC, HLS; Hand-on experience in FPGA design Experience with C-to-Silicon is a plus; Design accelerator logic in SV, SC, HLS; Map FPGA resources to design and close timing; Document design for SW/CSR interface, Design Spec, user guide *REQUIREMENT7*. Testcase development Develop initial testcases for both driver and HW test; Work with Validation/Verification team to come up with testplan to create test for PV coverage *REQUIREMENT8*. Simulation bring-up Bring-up ASE simulation for a given design *REQUIREMENT9. *Hardware bring-up / Debug Develop Hardware testplan; Collect hardware coverage *REQUIREMENT10* Validation/Verification Engineer 6+ years ; Strong background in IP-level Validation/Verification; AXI-3/4 experience; Performance benchmarking experience. -- You received this message because you are subscribed to the Google Groups "Visa Transfer OPT, CPT, PT, H1,H4" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at https://groups.google.com/group/paul_talluri. For more options, visit https://groups.google.com/d/optout.
