Ian,
Thanks for coming back.
The component with hidden pins came from an Orcad project, I think. The pins are assigned to the power nets in the component properties but have no net assigned on the PCB. If I make them visible they have no wire connection so I can't link them to the power rails. I could re-create the component but I would really like to get the schematics to inherit the nets from the PCB.
You want the Sch to inherit from the PCB? So if I get you right you want the Update Sch from PCB process to back-annotate the power nets from the PCB back to the hidden pins. I guess this would be possible but my assumption is that it is not currently done. I am note sure it is a wise idea either - I keep thinking of wonderful ways of stuffing up the design. Hidden pins are just that "hidden". Which makes checking them hard. I am not sure I would want automatic back-annotation of hidden pin connectivity from the PCB - but since I never use hidden pins I guess this is something I have not thought of a great deal.
If it was a project I was responsible for and I knew the conversion from Orcad to Protel was one way (never needing to go back) I would unhide the pins and wire up the power pins. If I knew it was going to go back to Orcad I would think long and hard about doing this anyway. A clear Sch in Protel is also a clear Sch in Orcad. But I digress into a soap-box subject of mine (hidden pins).
If it was me I would want the netlist to be correct - for me the netlist is driven by the Sch. So I would try to work out why the Sch-generated netlist was not doing what I expect.
(For those not familiar with DXP and P2004 - you can set the net that a hidden pin connects to. It is no longer just a forced connection to the net of the same name as the pin name as in P99SE and earlier.)
The Navigator panel will take a bit of getting used to as I don't yet know what is right and what is wrong but one pointer to the bus problem is that each wire on the unconnected busses has two entries; one has a scope of 'local to document' and the other is 'sheet interface'. How do I convince DPX to actually connect these two together?
There is a gotcha to do with net naming. If you have a port-named net (in DXP and P2004 ports and sheet entries can optionally name nets) and a net label named net on the same sheet (and they aren't wired together, that is they are not connected by a wire), these nets will *not* connect. This is because the port-named nets exist at a different level in the hierarchy compared to the net labeled named nets. There are good reasons why this is so and it has been discussed in some length on the DXP forum (a number of times). There is a warning about duplicate net names that should help trap the problem, but there can be so many warnings in a correct project that real issues can get swamped. I take the precaution of putting a net-label on the wire exiting the port to make sure the name is propagated correctly. (Back in the early days of DXP the duplicate net name waning was not working and this concept of port-labelled nets and net-labelled nets not joining came up a few times.) In P99SE ports and sheet entries can't label nets, the same problem exists but it is less confusing as you are not likely to see two net names that are the same.
Apart from that I dunno. I can't totally wrap my head around the problem with just words. And I haven't seen the problem before (or I can't recognise it from the words). Can you send the project?
I will no doubt cop all sorts of complaints but I suspect you would get a better response by 1) asking on the DXP forum where Altium employees are permitted to participate and there are more active DXP/P2004 users, and, 2) asking Altium directly.
DPX does not appear to have any documentation on resolving problems. When error messages come up there is nothing to indicate how to fix them. I would really like to know why the schematics can't be updated from the PCB
They can be but only some aspects of the Sch. I don't think anything to do with connectivity can be back-annotated from PCB to Sch. Only stuff like designators, footprints, comments etc. I am not sure there has been much change in what can be back-annotated from PCB to Sch compared to P99SE - maybe some rules or something like that but I can't recall anything. Altium people should be able to expand on this.
As for dealing with problems - always hard to write but I agree there is too little info about dealing with the problems that come up. The best (most concise) source I know of is the expanding Altium KB. Many questions asked on the DXP forum are collected and distilled into KB articles. This process has been weekly or monthly for a while now. A post is sent to the DXP forum listing the new articles. But if your problem has not come up and been addressed it is not likely to have appeared in the KB. It is worth a check though.
Something that annoys me is there is precious little info about the warnings and error messages that appear in the Message panel. Since Altium generated these error and warning messages it is reasonable that they should document and explain them - much like a decent compiler will document the compile and link errors it can emit.
Documenting problems that occur because of assumptions and behaviour by the user is harder to write about, of course. I guess one advantage of a strictly controlled design process (as I gather some other CAE systems enforce) is the scope of such problems is likely to be less.
Bye for now, Ian
Regards,
Dave
-----Original Message----- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Ian Wilson Sent: 18 October 2004 23:53 To: Protel EDA Discussion List Subject: Re: [PEDA] FW: A real DXP problem
On 05:51 PM 18/10/2004, Dave Courtney said: >OK I'll try the old email address > >I have a multi-sheet hierarchical design using ports to link connections and >busses via the top level schematic. I then had some problems creating the >PCB. Some busses were not included on the layout and the hidden pins used on >some imported components did not have the power connections assigned.
Dave,
Hidden pins have changed in DXP. I am not completely sure of the extent of the changes - but in DXP you have the option of setting which hidden pins are connected to what net. Editing the pin allows you to change this. I am not sure if this is part of your problem at all. Can't tell without seeing the design. I hate hidden pins and never use them, so I have not delved into their behaviour in DXP/P2004 at all. If I ever use an Altium component I copy into my own library and unhide all the hidden pins and remove the duplicates power pins from all but one part. (To me a improvement would be to simply not support hidden pin connectivity at all - this would be a feature in my book. But I know others use the concept. I just think it is not worth the problems in this day of switched rails and multiple supply voltages.)
As for the transfer of busses - there are limitations on busses in Protel products that have been there for ages and users have been asking for improvements. P2004 introduced bus joiners which allow you to collect dissimilar (non-bus) signals into a bus. **BUT** these only work in FPGA projects. Boy was I peeved when I found that out. Are your busses "Protel-correctly" formed? That is each nets is of the form BUS0, BUS1,... and the bus and ports labelled as BUS[0..15] (or whatever). There is a tutorial pdf on connectivity - not sure it may be targeting the different hierarchy modes though.
> To >make some progress I edited the missing pins on the PCB. Now, when I use the >'Update schematics' option, the comparator find the differences but states >'no updates are possible to Flattened Project'. How should I resolve the >discrepancies between the schematics and PCB?
Editing nets on the PCB is not what I would normally do but it should not itself cause a problem. The comparator should just spot the differences and offer to resolve them. If it is thinking that your manual edits added extra connections it should have just "offered" to remove them.
The Navigator panel is a good place to investigate netlist issues. What you see when browsing the design with the Navigator should be what is transferred to the PCB. Have you checked your designs connectivity with the Navigator panel?
If you are able to zip up and email your design to me I will have a quick look and see if I can spot anything obvious.
Have you sent the design to Altium and asked for their advice? They offer to do that pretty regularly for posters on their forum.
Ian
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