Low speed, 16Mhz, 50kSPs ADCs. Analog circuits need to be quarantined.
Regards, Steve
Great, a low speed circuit. If one of the main interface ICs is a high density FPGA, then you will have the luxury of routing to that particular IC any IO to any desired other IC pin.
My favorite optimize trick here is to make the schematic components, typically the FPGA, the same shape & pin orientation as it's IC package. Then, plan out the other ICs around the FPGA as you expect to fit it on the PCB.
When routing, do all the power VCC/GND/VCCint "via them out" first... & decoupling caps first keeping allowance for tracing.
Keep clocks signals on a separate layer only if needed. I typically put those on my VCCint layer.
Working along this route can give you something similar to the email photo I sent you directly.
Here is an extreme example of starting the layout from the schematic stage.
This is a 4 layer board, green is the top & red bottom, the traces are 8 mil, 8 mil gap & 10 mil via with 30 mil hole. PWR & GND traces from ICs are 12mil - 24 mil. Your looking at 64 bit SDRam (red-under FPGA), 1 via per ram signal, 240 pin FPGA, & 24 bit 200MHz RGB ADC (left - top) & 24 bit, 240 MHz RGB dac (right top). PCB has 3 signal layers, high speed on top & bottom, middle (blue) for signals at the 24 MHz range. 1 power filled plane (not shown) + polygon fills (not shown / filled in) on the 3 shown layer, (green,blue,red).
(If anyone else wants to see the 96kb photo file, email me directly with your email adderss -> [EMAIL PROTECTED]
____________ Brian Guralnick
----- Original Message ----- From: "Steve Allen" <[EMAIL PROTECTED]>
To: "Protel EDA Discussion List" <[EMAIL PROTECTED]>
Sent: Thursday, November 04, 2004 10:53 AM
Subject: Re: [PEDA] Board Layout Planning
All, thanks again. It's extremely helpful to lean on your experience!
>Did you create the schematic?
No. In fact, I don't have a copy of it yet. I suspect it'll need some cleanup. At present, I'm working off a preliminary BOM.
>Which size BGAs are you using? Must all your main ICs be BGA?
I agree. I've been working to limit BGA use that would force special board fabrication. I can always fall back to the BGA package is space requires it. I assume it would be preferable to add more layers than use blind vias?
176 pin, 0.8mm pitch, 12x12mm package:
This one would force me to special board fab techniques, I think, either blind vias or very aggressive fab (.015/.006 via). I convinced them to use the QFP package.
56 pin, .65mm pitch BGA: Tight pitch! This is switched to TSSOP package.
64 pin, 1mm, 10x13mm package: This is a keeper. It only comes in BGA, and I don't expect real difficult routing.
>Can you mount components on both sides of the PCB? Thankfully, yes. I'd like to place large body parts all on a common side.
>Do you have a main processor, or is it an FPGA, or, a processor with an
FPGA for SDram & bus control?
>To what % peak clock rate are you using in the FPGA/SDram combination,
are you using the DQMs?
>Do you have an analog AD/DA sections, do they need to be quarantined,
does it need to be on the same PCB?
Main processor, flash memory (1mm BGA), EEPROM, various communication devices, analog data acquisition.
Low speed, 16Mhz, 50kSPs ADCs.
Analog circuits need to be quarantined.
Regards, Steve
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