Hi Brad,
Thanks. I've solved the repour problem. The rule that I quoted
was the culprit. The "problem" now is the DRC violations that occur with
the remaining clearance rules. I think the difference now is my
clearance rule is set for Same Net Only whereas you chose different Nets
Only. I was trying to silence the DRC violations that occur for every
track and arc of the polygon. Hope that makes more sense.
Dan Enslen
The only reason time exists is so
everything doesn't happen all at once.
-----Original Message-----
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On Behalf Of Brad Velander
Sent: Friday, February 25, 2005 12:33 PM
To: Protel EDA Discussion List
Subject: RE: [PEDA] Polygon Pour Problem
Dan,
I am not sure that what you were trying to do is all that clear.
If I recall correctly you had your polygon set without the "Pour Over
Same Net" selected, but this rule you mention below seems to have been
set-up just to allow the pour to contact the same net. A little bit of a
conflict? Maybe this is why the polygon pour gagged on the rule.
Oh one tip for you, if you set your polygon grid size to "0", it
will pour the track widths edge to edge every time giving you a solid
polygon regardless of the track width.
Typically I write a generic polygon clearance rule like this. If
I want to pour over the same net I enable it through the polygon pour
window. I then have a clearance rule for Object Kind - polygon to Object
Kind - vias, tracks/Arcs, fills, keepouts, SMD pads, Thru-hole Pads;
Different Nets Only.
Sincerely,
Brad Velander
Senior PCB Designer
Northern Airborne Technology
1925 Kirschner Rd.,
Kelowna, BC, V1Y 4N7.
tel (250) 763-2329 ext. 225
fax (250) 762-3374
-----Original Message-----
From: Dan Enslen [mailto:[EMAIL PROTECTED]
Sent: Friday, February 25, 2005 9:17 AM
To: [email protected]
Subject: [PEDA] Polygon Pour Problem
Thanks to all,
Harry was on the right track with the clearance rule issue. I
think
I may have poured the polygon first, then created a specific rule to
silence
the DRC beast. This leads me to wonder how to set a rule for polygon
clearance issues. I typically set up my polygons for a solid fill. Phil
said
he uses wider tracks than gaps as does Protel's help section. In my case
I
was using 8mil tracks, 8 mil gaps and 5 mil min. The problem child rule
was:
Clearance Rule - Obj. kind > Polygons and Obj. kind > Tracks/Arcs set to
min. clearance > 0 mil, Same Net Only. In hindsight I'm not quite sure
why I
wrote it that way. It doesn't seem real intuitive now. Does anyone have
a
tried and true general rule that works in this instance?
Dan Enslen
Texas Instruments Tucson
520.746.7324
[EMAIL PROTECTED]
____________________________________________________________
You are subscribed to the PEDA discussion forum
To Post messages:
mailto:[email protected]
Unsubscribe and Other Options:
http://techservinc.com/mailman/listinfo/peda_techservinc.com
Browse or Search Old Archives (2001-2004):
http://www.mail-archive.com/[email protected]
Browse or Search Current Archives (2004-Current):
http://www.mail-archive.com/[email protected]
____________________________________________________________
You are subscribed to the PEDA discussion forum
To Post messages:
mailto:[email protected]
Unsubscribe and Other Options:
http://techservinc.com/mailman/listinfo/peda_techservinc.com
Browse or Search Old Archives (2001-2004):
http://www.mail-archive.com/[email protected]
Browse or Search Current Archives (2004-Current):
http://www.mail-archive.com/[email protected]
